help this verilog code! how pull code!

[liu_uestc]

always@(posedge s3 or posedge addpc);
begin
if(addpc) pc<=pctemp+1'b1;
else begin pc<=13'b0000000000111;pctemp<=pctemp+1'b1;end
end
warningctemp isn't the always control envent!
///////////////////////////////////////////////////////////////////////////////////////////////ffunction description:
pc adds one by addpc asynchronously ,pc becomes 13'b0000000000111on the rising edge of s3;
//////////////
how to modify?

 

[qiqi6416]

where did you define the pctemp? if it is a local declaration, then the sequential block requries a label.

 

[liu_uestc]

i define in module,where is local define,how to give a lable,?

Added after 5 minutes:

just one module ,one always,all the varials after
module

 

[Matrix_YL]

Hi liu_uestc
your codes are so confusing !

maybe you should modify like this
always@(posedge s3 or posedge addpc);
begin
if(s3)
begin
pc<=13'b0000000000111;
pctemp<=13'b0000000000111;
end //S3 is asynchro preset
else
pc<=pctemp+1'b1;
end