Help - sdf anottation using vcs

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chandhramohan

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sdf_annotate vcs

Hi ,
Need help on sdf annotation using vcs for gate level timing simulation .Is there any vcs userdefined task that will take the sdf file for the specified design top level.
Thanks for the help.

regards
mohan
 

$sdf_annotate func

chandhramohan said:
Hi ,
Need help on sdf annotation using vcs for gate level timing simulation .Is there any vcs userdefined task that will take the sdf file for the specified design top level.
Thanks for the help.

regards
mohan
Click to expand...
Mohan,
Did you try the standard $sdf_annotate stuff? Look for it in Google - or best in VCS manual. If you have specific issue, perhaps some one can help.

HTH
Ajeetha
www.noveldv.com
 

vcs sdf_annotate log file format

Hi Aji ,
Is this ($sdf_annotate ) a standard task or specific to ncverilog / Verilog XL .

Thanks
Mohan
 

$sdf_annotate in vcs

$sdf_annotate is a standard function of verilog. all verilog simulator can use it. include nc(xl), vcs & modelsim etc.
 

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