[help] rippled/gated clock warning

[iamczx]

Module A (input wire clk, 
input wire rst , 
.....
// other input,
output reg sram_clk,
...
// ohter sram control signal
);
...
//use FSM to produce the sram_clk signal
st0: sram_clk <= 1'b1;
st1: sram_clk <= 1'b0;
st2: sram_clk <= 1'b0;
st3: sram_clk <= 1'b1;

endmodule

Module B (input wire sram_clk,
//other controller signal);
....
endmodule

connect a.sram_clk to b.sram_clk.
when using quartus to compile these code ,the rippled/gated clock waring will be reported.
So, how should i constrain the sram_clk ? can I constrain multi cycle to sram_clk?
Anyway to produce better sram_clk signal?

thanks

 

[iamczx]

someone told me I should use sram_clk to be enable signal and use clk to drive the sram clk. Just like pic a shows.

but I am puzzled . If there are some delay with sram_clk, the new_clk (=sram_clk && clk) will work correctly? Just like pic b shows.
thanks