iamczx
Member level 3
Code:
Module A (input wire clk,
input wire rst ,
.....
// other input,
output reg sram_clk,
...
// ohter sram control signal
);
...
//use FSM to produce the sram_clk signal
st0: sram_clk <= 1'b1;
st1: sram_clk <= 1'b0;
st2: sram_clk <= 1'b0;
st3: sram_clk <= 1'b1;
endmodule
Module B (input wire sram_clk,
//other controller signal);
....
endmoduleconnect a.sram_clk to b.sram_clk.
when using quartus to compile these code ,the rippled/gated clock waring will be reported.
So, how should i constrain the sram_clk ? can I constrain multi cycle to sram_clk?
Anyway to produce better sram_clk signal?
thanks