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Help required in developing generic Verilog code

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er.akhilkumar

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Hello all,

I am trying to develop generic RTL, in which I am trying to load a memory of generic width and generic depth with input data which is smaller than memory width.

Suppose memory width is 32 and memory depth is 16, but input data width is 16-bit. Means to write one location of memory we need two write accesses. I will write this logic as:

always @(posedge clock) begin
if(writing)
case (address[0])
0: memory[address%2] [15:0] <= input_data;
1: memory[address%2] [31:16] <= input_data;
endcase
end


Now suppose input data width is 8 bit. Means now 4 accesses will be needed to write one location of memory. So now the code will be

always @(posedge clock) begin
if(writing)
case (address[1:0])
2'b00: memory[address%4] [7:0] <= input_data;
2'b01: memory[address%4] [15:8] <= input_data;
2'b10: memory[address%4] [23:16] <= input_data;
2'b01: memory[address%4] [31:24] <= input_data;
endcase
end


But this is totally a manual work, I need to develop a generic code. Can anyone please help me out how can we develop generic code for above logic? And it should be synthesizable also.

Thanx
 

kingslayer

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Hi!

I think the most easy way to do so is to write your own preprocessing script to generate the code you want according to some input parameter (in your case the data width). Since the code you are going to generate is very simple you won't have problems in writing a simple script. Then, invoke the script along the flow before going to synthesis.

Cheers
 
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