ellis91
Newbie level 6

Hi all,
I have a perfectly working test bench code. This is the code i've written :
ENTITY final_packet_format_error_detectiontest IS
END final_packet_format_error_detectiontest;
ARCHITECTURE behavior OF final_packet_format_error_detectiontest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT final_packet_format_error_detection
PORT(
data_receive : IN std_logic_vector(0 to 7);
clock : IN std_logic;
reset : inout STD_LOGIC ;
special_byte : IN std_logic_vector(0 to 7);
no_of_bytes: in STD_LOGIC_VECTOR(0 to 19);
no_error_bytes : inout STD_LOGIC_VECTOR(0 to 19) ;
no_special_bytes : inout STD_LOGIC_VECTOR(0 to 19);
byte_count : inout STD_LOGIC_VECTOR(0 to 19);
no_clock_cycles : inout STD_LOGIC_VECTOR(0 to 19);
no_data_packets_received : inout STD_LOGIC_VECTOR(0 to 19)
);
END COMPONENT;
--Inputs
signal data_receive : std_logic_vector(0 to 7) := (others => '0');
signal clock : std_logic ;
signal reset : STD_LOGIC;
signal special_byte : std_logic_vector(0 to 7) ;
signal no_of_bytes : STD_LOGIC_VECTOR(0 to 19);
--BiDirs
signal no_error_bytes : STD_LOGIC_VECTOR(0 to 19);
signal no_special_bytes : STD_LOGIC_VECTOR(0 to 19);
signal byte_count : STD_LOGIC_VECTOR(0 to 19):= (others => '0');
signal no_data_packets_received : STD_LOGIC_VECTOR(0 to 19);
signal no_clock_cycles : STD_LOGIC_VECTOR(0 to 19);
-- Clock period definitions
constant clock_period : time := 1 us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: final_packet_format_error_detection PORT MAP (
data_receive => data_receive,
clock => clock,
reset => reset,
special_byte => special_byte,
no_of_bytes => no_of_bytes,
no_error_bytes => no_error_bytes,
no_special_bytes => no_special_bytes,
byte_count => byte_count,
no_data_packets_received => no_data_packets_received,
no_clock_cycles => no_clock_cycles
);
-- Clock process definitions
clock_process
rocess
begin
clock <= '1';
wait for clock_period/2;
clock <= '0';
wait for clock_period/2;
end process;
process
begin
--special_byte refers to the byte you want as the start byte
special_byte <= "10000000";
--the variable- no_of_bytes refers to the number of data bytes(including '1' special byte) in a packet
no_of_bytes <= "00000000000000000101";
wait;
end process;
-- Stimulus process
stim_proc: process
begin
--adjust the initial RESET condition here. Reset condition can be triggered again during simulation
reset <= '0';
-- insert stimulus here
data_receive <= "10100000"; wait for 1 us;
data_receive <= "10010000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10110000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10011000"; wait for 1 us;
data_receive <= "10001000"; wait for 1 us;
data_receive <= "10001000"; wait for 1 us;
data_receive <= "10001000"; wait for 1 us;
data_receive <= "10001000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10001000"; wait for 1 us;
data_receive <= "10001000"; wait for 1 us;
data_receive <= "10010000"; wait for 1 us;
data_receive <= "10001000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10001000"; wait for 1 us;
end process;
END;
It is quite tedious typing in the input-data_receive each time i want a new input. One thing i can do to make it a little simpler is make the input clocked. That way i won't have to type in the "wait for 1 us" line. But i think it will be very convenient if i enable the test bench to read the inputs line by line from a ".txt" file. The code can do much more that way. How do i have to go about coding it? can i also program the inout ports to display data outputs in another ".txt"? Help will be highly appreciated. Thanks
I have a perfectly working test bench code. This is the code i've written :
ENTITY final_packet_format_error_detectiontest IS
END final_packet_format_error_detectiontest;
ARCHITECTURE behavior OF final_packet_format_error_detectiontest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT final_packet_format_error_detection
PORT(
data_receive : IN std_logic_vector(0 to 7);
clock : IN std_logic;
reset : inout STD_LOGIC ;
special_byte : IN std_logic_vector(0 to 7);
no_of_bytes: in STD_LOGIC_VECTOR(0 to 19);
no_error_bytes : inout STD_LOGIC_VECTOR(0 to 19) ;
no_special_bytes : inout STD_LOGIC_VECTOR(0 to 19);
byte_count : inout STD_LOGIC_VECTOR(0 to 19);
no_clock_cycles : inout STD_LOGIC_VECTOR(0 to 19);
no_data_packets_received : inout STD_LOGIC_VECTOR(0 to 19)
);
END COMPONENT;
--Inputs
signal data_receive : std_logic_vector(0 to 7) := (others => '0');
signal clock : std_logic ;
signal reset : STD_LOGIC;
signal special_byte : std_logic_vector(0 to 7) ;
signal no_of_bytes : STD_LOGIC_VECTOR(0 to 19);
--BiDirs
signal no_error_bytes : STD_LOGIC_VECTOR(0 to 19);
signal no_special_bytes : STD_LOGIC_VECTOR(0 to 19);
signal byte_count : STD_LOGIC_VECTOR(0 to 19):= (others => '0');
signal no_data_packets_received : STD_LOGIC_VECTOR(0 to 19);
signal no_clock_cycles : STD_LOGIC_VECTOR(0 to 19);
-- Clock period definitions
constant clock_period : time := 1 us;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: final_packet_format_error_detection PORT MAP (
data_receive => data_receive,
clock => clock,
reset => reset,
special_byte => special_byte,
no_of_bytes => no_of_bytes,
no_error_bytes => no_error_bytes,
no_special_bytes => no_special_bytes,
byte_count => byte_count,
no_data_packets_received => no_data_packets_received,
no_clock_cycles => no_clock_cycles
);
-- Clock process definitions
clock_process
begin
clock <= '1';
wait for clock_period/2;
clock <= '0';
wait for clock_period/2;
end process;
process
begin
--special_byte refers to the byte you want as the start byte
special_byte <= "10000000";
--the variable- no_of_bytes refers to the number of data bytes(including '1' special byte) in a packet
no_of_bytes <= "00000000000000000101";
wait;
end process;
-- Stimulus process
stim_proc: process
begin
--adjust the initial RESET condition here. Reset condition can be triggered again during simulation
reset <= '0';
-- insert stimulus here
data_receive <= "10100000"; wait for 1 us;
data_receive <= "10010000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10110000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10011000"; wait for 1 us;
data_receive <= "10001000"; wait for 1 us;
data_receive <= "10001000"; wait for 1 us;
data_receive <= "10001000"; wait for 1 us;
data_receive <= "10001000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10001000"; wait for 1 us;
data_receive <= "10001000"; wait for 1 us;
data_receive <= "10010000"; wait for 1 us;
data_receive <= "10001000"; wait for 1 us;
data_receive <= "10000000"; wait for 1 us;
data_receive <= "10001000"; wait for 1 us;
end process;
END;
It is quite tedious typing in the input-data_receive each time i want a new input. One thing i can do to make it a little simpler is make the input clocked. That way i won't have to type in the "wait for 1 us" line. But i think it will be very convenient if i enable the test bench to read the inputs line by line from a ".txt" file. The code can do much more that way. How do i have to go about coding it? can i also program the inout ports to display data outputs in another ".txt"? Help will be highly appreciated. Thanks