Kandarp Gandhi
Newbie level 2
Hello
I am writing a verilog code for a 8 bit ripple carry adder that transfers value of input a to a latch and then does the calculation.
However my code is perfect for a system without a latch but when I introduce a latch and a clock the code freaks out. Also in my simulation results the clock just does not start and remains undefined throughout.
Please let me know what could have bee the problem
I am writing a verilog code for a 8 bit ripple carry adder that transfers value of input a to a latch and then does the calculation.
However my code is perfect for a system without a latch but when I introduce a latch and a clock the code freaks out. Also in my simulation results the clock just does not start and remains undefined throughout.
Please let me know what could have bee the problem