Help needed with ripple carry adder!

[Kandarp Gandhi]

Hello

I am writing a verilog code for a 8 bit ripple carry adder that transfers value of input a to a latch and then does the calculation.
However my code is perfect for a system without a latch but when I introduce a latch and a clock the code freaks out. Also in my simulation results the clock just does not start and remains undefined throughout.

Please let me know what could have bee the problem

 

[K-J]

Please let me know what could have bee the problem

The first problem is that you posted no code for anyone to see what the other problems might be. Most here are not psychic.

Kevin Jennings

 

[Kandarp Gandhi]

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Code Verilog - [expand]
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timescale 1ns/10ps
module
 rca8(sum,c_out,a,b,c_in,clk);
input[7:0] a,b;
input c_in,clk;
output[7:0]sum;
output c_out;
reg [8:0]carry;
integer i;
reg[7:0] a_latch,b_latch;
reg c_latch;
 
always @(posedge clk) begin
a_latch=a;
b_latch=b;
c_latch=c_in;
end
  
wire [7:0]p = a_latch ^ b_latch;
wire [7:0]g = a_latch & b_latch;
 
always@(a_latch or b_latch or c_latch or p or g )
begin
carry[0]=c_latch;
 
for(i=1;i<=8;i=i+1) 
begin
carry[i]=g[i-1]|(p[i-1]&carry[i-1]);
end
 
end
 
wire [7:0] sum = p ^ carry;
wire c_out = carry[8];
 
endmodule

---

 

[ads-ee]

Ugh, what is with the poor formatting of code from new users?
I've always used some form of indentation and comments ever since writing FORTRAN & BASIC.

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Code Verilog - [expand]
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// timescale directives do not belong in RTL code, they
// should only be defined in the top level testbench.
// you were also missing the ` (back tick)
`timescale 1ns/10ps
 
// Antiquated pre 2001 syntax, use 2001 port definitions
// unless your simulator/synthesis tool is junk and can only
// support '95 (if so switch simulators)
module rca8 (sum,c_out,a,b,c_in,clk);
input  [7:0] a,b;
input        c_in,clk;
output [7:0] sum;
output       c_out;
// this is what you should write:
module rca8 (
  input  [7:0] a,    // and it allows per-port comments on the ports function
  input  [7:0] b,
  input        c_in,
  input        clk,
  output [7:0] sum,
  output       c_out
);
 
reg [8:0] carry;
integer i;
reg [7:0] a_latch, b_latch;
reg       c_latch;
 
// Use non-blocking (<=) in clocked always blocks, otherwise you
// may end up with a mismatch between simulation and synthesis if
// any of the RHS equations uses any of the LHS signals.
//
// Also why are you calling this a latch? Latches are combinatorial
// storage elements, while this is coded as a register.
always @ (posedge clk) begin
  a_latch <= a;
  b_latch <= b;
  c_latch <= c_in;
end
 
// I usually consider it bad practice to put signal declarations in the middle
// of code, if you ever decided to modify the code and use either p or g
// prior to this you'll end up with some sort of compilation error.
wire [7:0] p = a_latch ^ b_latch;
wire [7:0] g = a_latch & b_latch;
 
// Once again 2001 added a feature that you should use. 
always @ (*) begin
  carry[0] = c_latch;
 
  // why start at 1, start at 0 as it's more natural and makes the
  // indexes simpler.
  for(i=0;i<8;i=i+1) begin
    carry[i+1] = g[i] | (p[i] & carry[i]);
  end
end
 
// you should be assigning the outputs, instead of using the wire declarations.
assign sum = p ^ carry;
assign c_out = carry[8];
 
endmodule

---

In your testbench you need to drive your clock input clk.
e.g.

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Code Verilog - [expand]
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initial begin
  clk = 0;
  forever #5 clk = ~clk;  // #5 based on your timescale will give you a 10ns period clock
end

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Regards