Avysochin
Newbie
Hello dear
there are many examples of such use
but i have the errors:
COMP96 ERROR COMP96_0018: "Identifier expected." "testbench.vhd" 12 16
COMP96 ERROR COMP96_0018: "Identifier expected." "testbench.vhd" 13 16
could you advice me
there are many examples of such use
Rich (BB code):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity testbench is
Generic (
Nkeybus : positive := 8); -- input bus width
end testbench;
architecture tb of testbench is
signal key_i : in std_logic_vector (Nkeybus-1 downto 0) := (others => 'X');
signal key_o : out std_logic_vector (Nkeybus-1 downto 0);
but i have the errors:
COMP96 ERROR COMP96_0018: "Identifier expected." "testbench.vhd" 12 16
COMP96 ERROR COMP96_0018: "Identifier expected." "testbench.vhd" 13 16
could you advice me