Hi friends while i simulating my design i come across the following warning.
# ** Warning: (vsim-3533) [FOFIW] - No mcd channels available.
Failed to open file "D:/output/v_out/design.out" for writing.
design.out is the file that will generated from my verilog code.
I used
file=$fopen("D:/output/v_out/design.out"); in the code.. but the file is not generating after simualtion...
I am not very shure that you are doing right because I never worked with windows modelsim
but in unix if you want to open a file the command is following :=
file=$fopen("../output/v_out/design.out");