jiangnancai
Junior Member level 3
I'm designing a dynamic comparator these days,whose spec is as follows:
The resolution: 4mv
Speed: 5Mhz
Generally,comparator has two types of topolgy.
The first is open-loop amplifier,which is limited by its speed. So I use the second architecture: Preamplifier + Latch.
Now the simulation results show that the comparator can detect an input difference
voltage of 1mv. However I hadn't simulate the offset voltage .
My question is that:
How can I see the offset voltage.
If the offset voltage is larger than 1mv( resolution), then will it damage the comparator's resolution in the actually-operated comparators?
The last question is how can i solve this problem? The zuto-zero calibration for offset voltage???
Thanks a million~~
The resolution: 4mv
Speed: 5Mhz
Generally,comparator has two types of topolgy.
The first is open-loop amplifier,which is limited by its speed. So I use the second architecture: Preamplifier + Latch.
Now the simulation results show that the comparator can detect an input difference
voltage of 1mv. However I hadn't simulate the offset voltage .
My question is that:
How can I see the offset voltage.
If the offset voltage is larger than 1mv( resolution), then will it damage the comparator's resolution in the actually-operated comparators?
The last question is how can i solve this problem? The zuto-zero calibration for offset voltage???
Thanks a million~~