I am trying to design a comparator.

[HossamHamdy]

When I designed a comparator for sigma-delta ADC I obtain this output. anyone can tell me how I can improve the output and make it sharper?

 

[betwixt]

I'm afraid that's like saying "I designed a bicycle but fell off it, whats wrong?". We need at the very least a schematic.

Brian.

 

[barry]

You don't even tell us what that picture is.

 

[D.A.(Tony)Stewart]

serious lack of effort on defining results & design specs

? expectations, CMRR, bias error, tolerance error, stray leakage of C to positive feedback and feedthru.
? measurement method?
? lack of multiple node comparisons or even analytical results

 

[dick_freebird]

I think what you're seeing is clock feedthrough but I would not
worry about it unless it impacts LSB integrity. Like if the trailing
edge of the red trace was the "live edge" for any goings-on,
that looks like "indecision".

Clock feedthrough can be driven down by relaxing the clock
edge rate imposed on the clocked devices, but at some point
other "care-abouts" (like settling time) put a stop to that. Lower
node-Z helps but costs stage gain. And so on. Best to follow
the perturbations back from "where you care" and see where
they enter the signal chain as "noise" (cyclostationary, but still)
and what mitigations suggest themselves.