Help Needed in handling Reset Signal!!

[sakthikumaran87]

Guys,

Is it legal to add combinational logic in rst signal. I came across a code where they are ORing the chip rst with a flop output and using this new reset signal to reset a new flop. I feel that this is not legal and will face DFT and PD issues. Am i right?? Pl comment. It is somewat urgent.

 

[maulin sheth]

Guys,

Is it legal to add combinational logic in rst signal. I came across a code where they are ORing the chip rst with a flop output and using this new reset signal to reset a new flop. I feel that this is not legal and will face DFT and PD issues. Am i right?? Pl comment. It is somewat urgent.

As I know for DFT,We are mostly adding combinational logic for controlling any input pin whether it is Reset or CLOCK pin.so for DFT,that is not might be any issue.

 

[morris_mano]

Yes, all clocks and reset pins must be controllable during dft for coverage on respective logic. If you are using some combination logic for generating internal clocks and reset, you have to make sure, during dft the internal logic is not blocking the clock and reset signal to the scannable flops. Usually, if the logic is blocking you can add mux before the scannable flops clocks and reset that bypass internal logic and pass through clock and reset used in dft mode.

 

[jt_eaton]

Yes, all clocks and reset pins must be controllable during dft for coverage on respective logic. If you are using some combination logic for generating internal clocks and reset, you have to make sure, during dft the internal logic is not blocking the clock and reset signal to the scannable flops. Usually, if the logic is blocking you can add mux before the scannable flops clocks and reset that bypass internal logic and pass through clock and reset used in dft mode.

Adding a mux into reset is the solution of last resort. It will always work but you are not testing the same pathways that you use in mission mode. You can have a failure inside the mux so that the test passes but the chip doesn't work. Using a mux does not let you test the logic that is driving the reset port.

A better way is to create a atpg_asyncdisable signal and use that to block the synchronous paths into reset when active. You can test all the logic using the mission mode pathways.