module adder_DW01_add_0 ( A, B, CI, SUM, CO );
input [7:0] A;
input [7:0] B;
output [7:0] SUM;
input CI;
output CO;
wire [7:1] carry;
FA1D0BWP35CD3NMLVT U1_7 ( .A(A[7]), .B(B[7]), .CI(carry[7]), .CO(CO), .S(
SUM[7]) );
FA1D0BWP35CD3NMLVT U1_6 ( .A(A[6]), .B(B[6]), .CI(carry[6]), .CO(carry[7]),
.S(SUM[6]) );
FA1D0BWP35CD3NMLVT U1_5 ( .A(A[5]), .B(B[5]), .CI(carry[5]), .CO(carry[6]),
.S(SUM[5]) );
FA1D0BWP35CD3NMLVT U1_4 ( .A(A[4]), .B(B[4]), .CI(carry[4]), .CO(carry[5]),
.S(SUM[4]) );
FA1D0BWP35CD3NMLVT U1_3 ( .A(A[3]), .B(B[3]), .CI(carry[3]), .CO(carry[4]),
.S(SUM[3]) );
FA1D0BWP35CD3NMLVT U1_2 ( .A(A[2]), .B(B[2]), .CI(carry[2]), .CO(carry[3]),
.S(SUM[2]) );
FA1D0BWP35CD3NMLVT U1_1 ( .A(A[1]), .B(B[1]), .CI(carry[1]), .CO(carry[2]),
.S(SUM[1]) );
FA1D0BWP35CD3NMLVT U1_0 ( .A(A[0]), .B(B[0]), .CI(CI), .CO(carry[1]), .S(
SUM[0]) );
endmodule
module adder ( in1, in2, carry_in, sum, carry_out );
input [7:0] in1;
input [7:0] in2;
output [7:0] sum;
input carry_in;
output carry_out;
adder_DW01_add_0 U1 ( .A(in1), .B(in2), .CI(carry_in), .SUM(sum), .CO(
carry_out) );
endmodule