hope all of u njoying at ur best ! well i m a new member here & new to VLSI as well.. i m doing a project in Verilog i.e. implementing direct form FIR filter in Verilog. i need help in synchronizing the sampling period of ADC with that of the verilog code clock.....but i m not able to do so..can any one help me here ..
well... i m doing it a lill differently......ADC is been conded in Matlab.... & the that digitized signal is being used by Verilog code ..... i m getting the output..but thats not upto the mark.....so i guess i need to adjust the clock of verilog code ..... if u need then i can attach those file here...or can mail to u ....
hope all of u njoying at ur best ! well i m a new member here & new to VLSI as well.. i m doing a project in Verilog i.e. implementing direct form FIR filter in Verilog. i need help in synchronizing the sampling period of ADC with that of the verilog code clock.....but i m not able to do so..can any one help me here ..