mona_c
Junior Member level 1

code for fir filter xilinx verilog
Hi everyone
hope all of u njoying at ur best ! well i m a new member here & new to VLSI as well.. i m doing a project in Verilog i.e. implementing direct form FIR filter in Verilog. i need help in synchronizing the sampling period of ADC with that of the verilog code clock.....but i m not able to do so..can any one help me here ..
thanx in advance
take care
bye
Mona
Hi everyone
hope all of u njoying at ur best ! well i m a new member here & new to VLSI as well.. i m doing a project in Verilog i.e. implementing direct form FIR filter in Verilog. i need help in synchronizing the sampling period of ADC with that of the verilog code clock.....but i m not able to do so..can any one help me here ..
thanx in advance
take care
bye
Mona