# help needed..coding FIR filter in Verilog

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#### mona_c

##### Junior Member level 1
code for fir filter xilinx verilog

Hi everyone

hope all of u njoying at ur best ! well i m a new member here & new to VLSI as well.. i m doing a project in Verilog i.e. implementing direct form FIR filter in Verilog. i need help in synchronizing the sampling period of ADC with that of the verilog code clock.....but i m not able to do so..can any one help me here ..

take care
bye
Mona

#### echo47

verilog fir xilinx

The common technique is to design one timing sequencer that controls both the FIR filter and the ADC, so you have full control of everything.

#### mona_c

##### Junior Member level 1
echo47 said:

The common technique is to design one timing sequencer that controls both the FIR filter and the ADC, so you have full control of everything.

Hi

well... i m doing it a lill differently......ADC is been conded in Matlab.... & the that digitized signal is being used by Verilog code ..... i m getting the output..but thats not upto the mark.....so i guess i need to adjust the clock of verilog code ..... if u need then i can attach those file here...or can mail to u ....

thanx
take care
bye
Mona

#### GroundCtrl

##### Junior Member level 3
First u have to do then u begining your new VLSI design is to search final solution of your problem in Xilinx and Altera sites )

There are several Verilog examples of FIR on Xilinx site.

#### mona_c

##### Junior Member level 1
hey i have seen these sites..but the prob is i have to code it at behavoural level at my own...... not in system verilog ...or with lrms & all

can u any onw help me ..plzzzz

bye
take care
Mona

#### nijMcnij

##### Full Member level 1
hello,

could you please point out exactly where in the Xilinx website the verilog example code for filter RTL implementation can be found.

many thanks

#### vleminh

##### Newbie level 4
hi all friends ! hi nijMcnij can you posts link of sites xilinx for me ?
Code:
[url][/url]

#### Rishabh Bansal

##### Newbie level 1
Re: code for fir filter xilinx verilog

Hi everyone

hope all of u njoying at ur best ! well i m a new member here & new to VLSI as well.. i m doing a project in Verilog i.e. implementing direct form FIR filter in Verilog. i need help in synchronizing the sampling period of ADC with that of the verilog code clock.....but i m not able to do so..can any one help me here ..

take care
bye
Mona

please send me code if you are having

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