I have read your paper, nice work btw. However, I think that resistors are probably the source of your problem. I dont see anywhere in you paper discussion on resistor process variations, This well resistor you used in osc have huge process variation (as 30%), you also use resistors to generate Vctrl and inside LDOs. Did you also simulate resistors over corners and MC? Maybe your models for resistors are bad, you should try to run MC just with resistor models set up to MC (for the rest you take typ) to see wheter they are OK.