Help Need: Please help me to understand this code

tokwatbaboy · Mar 22, 2015

Not a RTL coder but I need to understand this piece of code:

finalGater = scanEn ? testModeEn: ~scanEn ? funcMode : 1'hx;

what does it means? any sample code/syntax I can use as reference?

thanks!

dave_59 · Mar 22, 2015

See section 11.4.11 Conditional operator of the IEEE 1800-2012 LRM.

tokwatbaboy · Mar 22, 2015

Thank you! Appreciate for pointing me the document.

mrflibble · Mar 22, 2015

tokwatbaboy said:
finalGater = scanEn ? testModeEn: ~scanEn ? funcMode : 1'hx;

And regarding code readability, personally I'd write that like so:

Code SystemVerilog - [expand]
1
finalGater = scanEn ? testModeEn : (~scanEn ? funcMode : 1'hx);

That way it's easier to see how the ~scanEn ? funcMode : 1'hx part of the expression is evaluated. Not just for yourself, but also for future victims. Even if that future victim is future you.

Help Need: Please help me to understand this code

tokwatbaboy

Newbie level 6

dave_59

Advanced Member level 3

tokwatbaboy

Newbie level 6

mrflibble

Advanced Member level 5

Similar threads

Code SystemVerilog - [expand]
1	finalGater = scanEn ? testModeEn : (~scanEn ? funcMode : 1'hx);

Help Need: Please help me to understand this code

tokwatbaboy

Newbie level 6

dave_59

Advanced Member level 3

tokwatbaboy

Newbie level 6

mrflibble

Advanced Member level 5

Similar threads

Privacy & Transparency

Privacy & Transparency