Help Need: Please help me to understand this code

[tokwatbaboy]

Not a RTL coder but I need to understand this piece of code:

finalGater = scanEn ? testModeEn: ~scanEn ? funcMode : 1'hx;

what does it means? any sample code/syntax I can use as reference?

thanks!

 

[dave_59]

See section 11.4.11 Conditional operator of the IEEE 1800-2012 LRM.

 

[tokwatbaboy]

Thank you! Appreciate for pointing me the document.

 

[mrflibble]

finalGater = scanEn ? testModeEn: ~scanEn ? funcMode : 1'hx;

And regarding code readability, personally I'd write that like so:

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Code SystemVerilog - [expand]
1
finalGater = scanEn ? testModeEn : (~scanEn ? funcMode : 1'hx);

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That way it's easier to see how the ~scanEn ? funcMode : 1'hx part of the expression is evaluated. Not just for yourself, but also for future victims. Even if that future victim is future you.