Re: shift register
I write a simple testbench, and you can write a more comprehensive testbench.
entity tb_shift_register4 is
end entity tb_shift_register4;
architecture behav of tb_shift_register4 is
signal reset: std_logic:='1';
signal clk : std_logic:='0';
signal si : std_logic;
signal s0 : std_logic;
signal q : std_logic_vector(3 downto 0);
signal cnt8 : unsigned(2 downto 0);
signal temp : unsigned(7 downto 0);
CONSTANT ONE_B_FS :time:= 1000000000.0000 fs;
CONSTANT Fclk :real:= 155.62;
CONSTANT Tclk :time:= ONE_B_FS/Fclk;
begin
shift_u: shift_register4(reset=>reset,clk=>clk,si=>si,s0=>s0,q=>q);
reset <= '1' after 10 ns;
clk <= not clk after Tclk/2;
process(reset,clk)
begin
if reset = '1' then
cnt8 <= (others=>'0');
temp <= (others=>'0');
elsif clk'event and clk = '1' then
cnt8 <= cnt8 + 1;
temp <= temp + 1;
end if;
end process;
si <= temp(7) when cnt8 = 7 else
temp(6) when cnt8 = 6 else
temp(5) when cnt8 = 5 else
temp(4) when cnt8 = 4 else
temp(3) when cnt8 = 3 else
temp(2) when cnt8 = 2 else
temp(1) when cnt8 = 1 else
temp(0) when cnt8 = 0 else
'0';
end behav;