anniemanuja
Newbie level 4
Hi frendz i have recvd a task. Plz help me how shall I approach the problem.. its SPI in VHDL
Instructions:
Write a VHDL program that implements a SPI interface to a CPU, the received bytes are passed to a command parser for decoding.
serial protocol in the SPI should be as follows:
1- /CS goes low prior to data transmittion
2-DCL rising edge is used to clock in the serial data
3-bit 0 is sent first, followed by bit 1, etc
4-the first byte received is a command, following bytes are data
5-/CS goes high at the end of each transaction
When a command is received by the SPI block it should put the command in the DFC bus and toggle the RDY line to trigger the parser.
The parser reads the command and sets high one of the command decode lines, there should be as many lines as commands.
If the command is a write command, the bytes following it are data, if the command is a read command the FPGA should send the content of the DTC bus to the CPU. At the end of the transmission of each byte the AUTO_INCREMENT line should toggle for one system clock (this will increment the memory pointer so burst reads are possible)
Write and simulate the assignment using any of the VHDL tool suites available to you.
Turn in source code, test bench source code, and simulation results through WebCT. Do a screen capture if you must and submit it as your simulation results. Make sure that all relevant signals are visible.
Instructions:
Write a VHDL program that implements a SPI interface to a CPU, the received bytes are passed to a command parser for decoding.
serial protocol in the SPI should be as follows:
1- /CS goes low prior to data transmittion
2-DCL rising edge is used to clock in the serial data
3-bit 0 is sent first, followed by bit 1, etc
4-the first byte received is a command, following bytes are data
5-/CS goes high at the end of each transaction
When a command is received by the SPI block it should put the command in the DFC bus and toggle the RDY line to trigger the parser.
The parser reads the command and sets high one of the command decode lines, there should be as many lines as commands.
If the command is a write command, the bytes following it are data, if the command is a read command the FPGA should send the content of the DTC bus to the CPU. At the end of the transmission of each byte the AUTO_INCREMENT line should toggle for one system clock (this will increment the memory pointer so burst reads are possible)
Write and simulate the assignment using any of the VHDL tool suites available to you.
Turn in source code, test bench source code, and simulation results through WebCT. Do a screen capture if you must and submit it as your simulation results. Make sure that all relevant signals are visible.