Help me write a SPI interface for CPU in VHDL

[anniemanuja]

Hi frendz i have recvd a task. Plz help me how shall I approach the problem.. its SPI in VHDL

Instructions:
Write a VHDL program that implements a SPI interface to a CPU, the received bytes are passed to a command parser for decoding.

serial protocol in the SPI should be as follows:

1- /CS goes low prior to data transmittion
2-DCL rising edge is used to clock in the serial data
3-bit 0 is sent first, followed by bit 1, etc
4-the first byte received is a command, following bytes are data
5-/CS goes high at the end of each transaction

When a command is received by the SPI block it should put the command in the DFC bus and toggle the RDY line to trigger the parser.

The parser reads the command and sets high one of the command decode lines, there should be as many lines as commands.

If the command is a write command, the bytes following it are data, if the command is a read command the FPGA should send the content of the DTC bus to the CPU. At the end of the transmission of each byte the AUTO_INCREMENT line should toggle for one system clock (this will increment the memory pointer so burst reads are possible)

Write and simulate the assignment using any of the VHDL tool suites available to you.

Turn in source code, test bench source code, and simulation results through WebCT. Do a screen capture if you must and submit it as your simulation results. Make sure that all relevant signals are visible.

 

[eject]

vhdl spi

Plz see www.mxic.com.tw
for 25xx series
ther are free model download

 

[maksya]

vhdl spi interface

Plz see www.mxic.com.tw
for 25xx series
ther are free model download

Can you give a direct link for download? The site's traffic is awful.

 

[Iouri]

spi vhdl code

https://www.xilinx.com/bvdocs/appnotes/xapp348.pdf


https://www.xilinx.com/bvdocs/appnotes/xapp386.pdf

they also provide source code

 

[eject]

spi interface vhdl

MX25L512 - 512Kb SPI Flash Model

http://www.mxic.com.tw/QuickPlace/hq/PageLibrary48256F5500439ED0.nsf/h_CE4C9490FDF4280B48256F550043C6D8/027603E0348A83C04825704D001FB451/$File/mx25L512.v?OpenElement

 

[rockgird]

Re: SPI in VHDL

hello, the link you've provided is probably not full ... coz its not pointing to any location ..

if u can plz generate a tinyurl from tinyurl.com or any such site ... that would be helpful

Added after 3 minutes:

i've found the link ... here it is

**broken link removed**

 

[HDXPY]

SPI in VHDL

Hi guys , an SPI interface is very useful.
I have developed a slave part using a Spartan 3 XC3S200-5tq144, trying to communicate the FPGA to a PIC32(master), but I have problems.
The PIC32 sends me a chain of characters by the SPI, the FPGA receives and sends them to a PC, then I verify the result using the hyperterminal.
The problem is that some bytes are not well received and I think it is because my SPI slave code that is the following
library ieee;
use ieee.std_logic_1164.all;

entity SLAVE_SPI is

port( reset : in std_logic;
SCLK : in std_logic;
MOSI : in std_logic;
MISO ut std_logic;
SS : in std_logic;
Dataout ut std_logic_vector(7 downto 0));
end SLAVE_SPI;

architecture Behavioral of SLAVE_SPI is
signal Shreg: std_logic_vector(7 downto 0):="10010101";
begin
--this process will strobe the received data (in Shreg)
process(reset, SS)
begin
if reset = '1' then
Dataout<="00000000";
elsif rising_edge(SS) then
Dataout<=Shreg;
end if;
end process;

MISO<=Shreg(7) when SS='0' --MISO<=Data when active
else 'Z'; --MISO<=High impedance otherwise

--The Slave will only be active when SS='0'
process(SS,SCLK)
begin
if SS='0' then
if rising_edge(SCLK) then
Shreg<=Shreg(6 downto 0)& MOSI;
end if;
end if;
end process;

end Behavioral;

Data_out is used to send the data to a PC at 115200baud.IN addition , I have verified that the master part develop in the PIC 32 is OK. ...so I guess the problem is in the side of the FPGA.

Please help me , I will really apreciate any comments you give....

 

[goalkeeper_buffon]

Re: SPI in VHDL

Hey HDXPY, do you actually have the master part of your code? It would be great if I can have a look on here as well along with the slave part. thanks