SPI in VHDL
Hi guys , an SPI interface is very useful.
I have developed a slave part using a Spartan 3 XC3S200-5tq144, trying to communicate the FPGA to a PIC32(master), but I have problems.
The PIC32 sends me a chain of characters by the SPI, the FPGA receives and sends them to a PC, then I verify the result using the hyperterminal.
The problem is that some bytes are not well received and I think it is because my SPI slave code that is the following
library ieee;
use ieee.std_logic_1164.all;
entity SLAVE_SPI is
port( reset : in std_logic;
SCLK : in std_logic;
MOSI : in std_logic;
MISO
ut std_logic;
SS : in std_logic;
Dataout
ut std_logic_vector(7 downto 0));
end SLAVE_SPI;
architecture Behavioral of SLAVE_SPI is
signal Shreg: std_logic_vector(7 downto 0):="10010101";
begin
--this process will strobe the received data (in Shreg)
process(reset, SS)
begin
if reset = '1' then
Dataout<="00000000";
elsif rising_edge(SS) then
Dataout<=Shreg;
end if;
end process;
MISO<=Shreg(7) when SS='0' --MISO<=Data when active
else 'Z'; --MISO<=High impedance otherwise
--The Slave will only be active when SS='0'
process(SS,SCLK)
begin
if SS='0' then
if rising_edge(SCLK) then
Shreg<=Shreg(6 downto 0)& MOSI;
end if;
end if;
end process;
end Behavioral;
Data_out is used to send the data to a PC at 115200baud.IN addition , I have verified that the master part develop in the PIC 32 is OK. ...so I guess the problem is in the side of the FPGA.
Please help me , I will really apreciate any comments you give....