Help me with writing a VHDL code

library ieee;
use ieee.std_logic_1164.all;

entity sequncer is
  
  port (
    event : in  std_logic;
    rst   : in  std_logic;
    v1    : out std_logic;
    v2    : out std_logic;
    v3    : out std_logic;
    v4    : out std_logic);

end sequncer;

architecture behave of sequncer is
signal shift_pos : std_logic_vector(3 downto 0);
signal shift_neg : std_logic_vector(3 downto 0);

begin  -- behave
  v1 <= not shift_pos(0) or shift_neg(0);
  v2 <= not shift_pos(1) or shift_neg(1);
  v3 <= not shift_pos(2) or shift_neg(2);
  v4 <= not shift_pos(3) or shift_neg(3);
  
positve_edge: process (event, rst)
begin  -- process positve-edge
  if rst = '0' then                     -- asynchronous reset (active low)
    shift_pos <= (others => '0')
  elsif event'event and event = '1' then  -- rising clock edge
    shift_pos <= shift_pos(2 downto 0)&shift_pos(3);
  end if;
end process positve_edge;

neg_edge: process (event, rst)
begin  -- process neg_edge
  if rst = '0' then                     -- asynchronous reset (active low)
    shift_neg <= (others => '1')
  elsif event'event and event = '0' then  -- rising clock edge
    shift_neg(0) <= shift_neg(2 downto 0)& shift_neg(3);
  end if;
end process neg_edge;
  

end behave;