Help me with writing a VHDL code

[voho]

help in vhdl

Hi all,


How to do this in vhdl ? Event is input signal


event___ ____________ ____________ ____________ _____
| | | | | | | |
|__ | |__| |__| |__|


V1______ _____________________________________________________
| |
|__|



V2______________________ _____________________________________
| |
|__|


V3______________________________________ _____________________
| |
|__|

V4______________________________________________________ _____
| |
|__|
Thank's in advance

Regards

 

[EDALIST]

Re: help in vhdl

can you just explain what are you trying to do, the diagram drawing is ver unclear ?

 

[foy]

help in vhdl

do you want to do what ？

 

[tkbits]

Re: help in vhdl

And what happens after V4?
Do you repeat from the start?

How to do this in vhdl ? Event is input signal

event___      ____________     ____________     ____________     _____
	     |     |		       |    |		         |    |		           |   |
	     |__ |		      |__|		      |__|		      |__|


V1______     _____________________________________________________
	      |    |
	      |__|



V2______________________    _____________________________________
			                  |   |
			                  |__|
	

V3______________________________________     _____________________
					                              |    |
					                              |__|

V4______________________________________________________     _____
							                                          |   |
							                                          |__|

 

[maksya]

help in vhdl

I think that the algorithm is something like that:

For every rising edge of event signal we will have to increment a coutner (0,1,2,3,0,1...). The counter's output is the address input of the demultiplexer. And the input of demultiplexer is the event.

voho, Is it so?

 

[voho]

Re: help in vhdl

thank'a all for your help,

I want to do this in first event i generate event (pulse)in V1, second event i generate event inV2, third event i generate event in V3

regards

 

[sp_harikrish]

Re: help in vhdl

Hi,
it looks like a shifted signal on each rising edge of the clock.
you can use shift register in this case.

 

[nand_gates]

Re: help in vhdl

Checkout the code below!
Hope this helps!

library ieee;
use ieee.std_logic_1164.all;

entity sequncer is
  
  port (
    event : in  std_logic;
    rst   : in  std_logic;
    v1    : out std_logic;
    v2    : out std_logic;
    v3    : out std_logic;
    v4    : out std_logic);

end sequncer;

architecture behave of sequncer is
signal shift_pos : std_logic_vector(3 downto 0);
signal shift_neg : std_logic_vector(3 downto 0);

begin  -- behave
  v1 <= not shift_pos(0) or shift_neg(0);
  v2 <= not shift_pos(1) or shift_neg(1);
  v3 <= not shift_pos(2) or shift_neg(2);
  v4 <= not shift_pos(3) or shift_neg(3);
  
positve_edge: process (event, rst)
begin  -- process positve-edge
  if rst = '0' then                     -- asynchronous reset (active low)
    shift_pos <= (others => '0')
  elsif event'event and event = '1' then  -- rising clock edge
    shift_pos <= shift_pos(2 downto 0)&shift_pos(3);
  end if;
end process positve_edge;

neg_edge: process (event, rst)
begin  -- process neg_edge
  if rst = '0' then                     -- asynchronous reset (active low)
    shift_neg <= (others => '1')
  elsif event'event and event = '0' then  -- rising clock edge
    shift_neg(0) <= shift_neg(2 downto 0)& shift_neg(3);
  end if;
end process neg_edge;
  

end behave;