help me with verilog code

mailan said:

,.here is a top module for a counter in verilog language.
but dont know to solve the errors,plss help me

ERROR:HDLCompilers:246 - "program_counter_top.v" line 48 Reference to vector reg 'seg_ones' is not a legal net lvalue
ERROR:HDLCompilers:102 - "program_counter_top.v" line 48 Connection to output port 'seg_ones' must be a net lvalue
ERROR:HDLCompilers:246 - "program_counter_top.v" line 49 Reference to vector reg 'seg_tens' is not a legal net lvalue
ERROR:HDLCompilers:102 - "program_counter_top.v" line 49 Connection to output port 'seg_tens' must be a net lvalue
ERROR:HDLCompilers:246 - "program_counter_top.v" line 50 Reference to vector reg 'sw_ones_temp' is not a legal net lvalue
ERROR:HDLCompilers:102 - "program_counter_top.v" line 50 Connection to output port 'sw_ones_temp' must be a net lvalue
ERROR:HDLCompilers:246 - "program_counter_top.v" line 51 Reference to vector reg 'sw_tens_temp' is not a legal net lvalue
ERROR:HDLCompilers:102 - "program_counter_top.v" line 51 Connection to output port 'sw_tens_temp' must be a net lvalue
ERROR:HDLCompilers:246 - "program_counter_top.v" line 52 Reference to vector reg 'ones_keepseg' is not a legal net lvalue
ERROR:HDLCompilers:102 - "program_counter_top.v" line 52 Connection to output port 'ones_keepseg' must be a net lvalue
ERROR:HDLCompilers:246 - "program_counter_top.v" line 53 Reference to vector reg 'tens_keepseg' is not a legal net lvalue
ERROR:HDLCompilers:102 - "program_counter_top.v" line 53 Connection to output port 'tens_keepseg' must be a net lvalue

here's the code:
module program_counter_top(
input clk,
input rst,
input incr,
input decr,
input start_stop,
input load,
input [3:0] sw_ones,
input [2:0] sw_tens,
output reg [6:0] seg_ones,
output reg [6:0] seg_tens,
output reg [3:0] sw_ones_temp,
output reg [2:0] sw_tens_temp,
output reg [3:0] ones_keepseg,
output reg [3:0] tens_keepseg
);

//wire clk_dv;
reg [3:0] loadnxt_ones;
reg [3:0] loadnxt_tens;
wire slow_clk;

//Instantiate the module
/* pc_dcm_clkdvr D1(
.CLKIN_IN (clk),
.RST_IN (rst),
.CLKDV_OUT (clk_dv),
.CLKIN_IBUFG_OUT(),
.CLKO_OUT(),
.LOCKED_OUT (lock)
);
*/
clk_divider_pc CDPC(
.clk (clk_dv),
.rst (rst),
.slow_clk (slow_clk)
);

program_counter ProgCount(
.clk (clk),
.rst (rst),
.incr (incr),
.decr (decr),
.start_stop (start_stop),
.load (load),
.sw_ones (sw_ones),
.sw_tens (sw_tens),
.seg_ones (seg_ones),
.seg_tens (seg_tens),
.sw_ones_temp (sw_ones_temp),
.sw_tens_temp (sw_tens_temp),
.ones_keepseg (ones_keepseg),
.tens_keepseg (tens_keepseg)
//.loadnxt_ones (loadnxt_ones),
//.loadnxt_tens (loadnxt_tens)
);

endmodule

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aruipksni said:

i think you probebly should not write output reg "signal".

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