Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

help me with verilog code

Status
Not open for further replies.

mailan

Newbie level 6
Joined
Jun 11, 2013
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
91
,.here is a top module for a counter in verilog language.
but dont know to solve the errors,plss help me

ERROR:HDLCompilers:246 - "program_counter_top.v" line 48 Reference to vector reg 'seg_ones' is not a legal net lvalue
ERROR:HDLCompilers:102 - "program_counter_top.v" line 48 Connection to output port 'seg_ones' must be a net lvalue
ERROR:HDLCompilers:246 - "program_counter_top.v" line 49 Reference to vector reg 'seg_tens' is not a legal net lvalue
ERROR:HDLCompilers:102 - "program_counter_top.v" line 49 Connection to output port 'seg_tens' must be a net lvalue
ERROR:HDLCompilers:246 - "program_counter_top.v" line 50 Reference to vector reg 'sw_ones_temp' is not a legal net lvalue
ERROR:HDLCompilers:102 - "program_counter_top.v" line 50 Connection to output port 'sw_ones_temp' must be a net lvalue
ERROR:HDLCompilers:246 - "program_counter_top.v" line 51 Reference to vector reg 'sw_tens_temp' is not a legal net lvalue
ERROR:HDLCompilers:102 - "program_counter_top.v" line 51 Connection to output port 'sw_tens_temp' must be a net lvalue
ERROR:HDLCompilers:246 - "program_counter_top.v" line 52 Reference to vector reg 'ones_keepseg' is not a legal net lvalue
ERROR:HDLCompilers:102 - "program_counter_top.v" line 52 Connection to output port 'ones_keepseg' must be a net lvalue
ERROR:HDLCompilers:246 - "program_counter_top.v" line 53 Reference to vector reg 'tens_keepseg' is not a legal net lvalue
ERROR:HDLCompilers:102 - "program_counter_top.v" line 53 Connection to output port 'tens_keepseg' must be a net lvalue

here's the code:
module program_counter_top(
input clk,
input rst,
input incr,
input decr,
input start_stop,
input load,
input [3:0] sw_ones,
input [2:0] sw_tens,
output reg [6:0] seg_ones,
output reg [6:0] seg_tens,
output reg [3:0] sw_ones_temp,
output reg [2:0] sw_tens_temp,
output reg [3:0] ones_keepseg,
output reg [3:0] tens_keepseg
);

//wire clk_dv;
reg [3:0] loadnxt_ones;
reg [3:0] loadnxt_tens;
wire slow_clk;

//Instantiate the module
/* pc_dcm_clkdvr D1(
.CLKIN_IN (clk),
.RST_IN (rst),
.CLKDV_OUT (clk_dv),
.CLKIN_IBUFG_OUT(),
.CLKO_OUT(),
.LOCKED_OUT (lock)
);
*/
clk_divider_pc CDPC(
.clk (clk_dv),
.rst (rst),
.slow_clk (slow_clk)
);

program_counter ProgCount(
.clk (clk),
.rst (rst),
.incr (incr),
.decr (decr),
.start_stop (start_stop),
.load (load),
.sw_ones (sw_ones),
.sw_tens (sw_tens),
.seg_ones (seg_ones),
.seg_tens (seg_tens),
.sw_ones_temp (sw_ones_temp),
.sw_tens_temp (sw_tens_temp),
.ones_keepseg (ones_keepseg),
.tens_keepseg (tens_keepseg)
//.loadnxt_ones (loadnxt_ones),
//.loadnxt_tens (loadnxt_tens)
);

endmodule
 

mrflibble

Advanced Member level 5
Joined
Apr 19, 2010
Messages
2,724
Helped
679
Reputation
1,360
Reaction score
651
Trophy points
1,393
Activity points
19,551
1 - you didn't include all your code, so no idea what you did wrong
2 - you didn't include all your code, so no idea what you did wrong
3 - try to include all your code, so we can see what you did wrong

You instantiate a program_counter module, but it's not declared anywhere. Also, you can use CODE tags to keep your posts with code in it a bit more readable. Most notably, the indentation will remain intact.
 

aruipksni

Full Member level 6
Joined
May 23, 2013
Messages
346
Helped
68
Reputation
136
Reaction score
66
Trophy points
1,308
Activity points
3,004
,.here is a top module for a counter in verilog language.
but dont know to solve the errors,plss help me

ERROR:HDLCompilers:246 - "program_counter_top.v" line 48 Reference to vector reg 'seg_ones' is not a legal net lvalue
ERROR:HDLCompilers:102 - "program_counter_top.v" line 48 Connection to output port 'seg_ones' must be a net lvalue
ERROR:HDLCompilers:246 - "program_counter_top.v" line 49 Reference to vector reg 'seg_tens' is not a legal net lvalue
ERROR:HDLCompilers:102 - "program_counter_top.v" line 49 Connection to output port 'seg_tens' must be a net lvalue
ERROR:HDLCompilers:246 - "program_counter_top.v" line 50 Reference to vector reg 'sw_ones_temp' is not a legal net lvalue
ERROR:HDLCompilers:102 - "program_counter_top.v" line 50 Connection to output port 'sw_ones_temp' must be a net lvalue
ERROR:HDLCompilers:246 - "program_counter_top.v" line 51 Reference to vector reg 'sw_tens_temp' is not a legal net lvalue
ERROR:HDLCompilers:102 - "program_counter_top.v" line 51 Connection to output port 'sw_tens_temp' must be a net lvalue
ERROR:HDLCompilers:246 - "program_counter_top.v" line 52 Reference to vector reg 'ones_keepseg' is not a legal net lvalue
ERROR:HDLCompilers:102 - "program_counter_top.v" line 52 Connection to output port 'ones_keepseg' must be a net lvalue
ERROR:HDLCompilers:246 - "program_counter_top.v" line 53 Reference to vector reg 'tens_keepseg' is not a legal net lvalue
ERROR:HDLCompilers:102 - "program_counter_top.v" line 53 Connection to output port 'tens_keepseg' must be a net lvalue

here's the code:
module program_counter_top(
input clk,
input rst,
input incr,
input decr,
input start_stop,
input load,
input [3:0] sw_ones,
input [2:0] sw_tens,
output reg [6:0] seg_ones,
output reg [6:0] seg_tens,
output reg [3:0] sw_ones_temp,
output reg [2:0] sw_tens_temp,
output reg [3:0] ones_keepseg,
output reg [3:0] tens_keepseg
);

//wire clk_dv;
reg [3:0] loadnxt_ones;
reg [3:0] loadnxt_tens;
wire slow_clk;

//Instantiate the module
/* pc_dcm_clkdvr D1(
.CLKIN_IN (clk),
.RST_IN (rst),
.CLKDV_OUT (clk_dv),
.CLKIN_IBUFG_OUT(),
.CLKO_OUT(),
.LOCKED_OUT (lock)
);
*/
clk_divider_pc CDPC(
.clk (clk_dv),
.rst (rst),
.slow_clk (slow_clk)
);

program_counter ProgCount(
.clk (clk),
.rst (rst),
.incr (incr),
.decr (decr),
.start_stop (start_stop),
.load (load),
.sw_ones (sw_ones),
.sw_tens (sw_tens),
.seg_ones (seg_ones),
.seg_tens (seg_tens),
.sw_ones_temp (sw_ones_temp),
.sw_tens_temp (sw_tens_temp),
.ones_keepseg (ones_keepseg),
.tens_keepseg (tens_keepseg)
//.loadnxt_ones (loadnxt_ones),
//.loadnxt_tens (loadnxt_tens)
);

endmodule

i think you probebly should not write output reg "signal".
 

mrflibble

Advanced Member level 5
Joined
Apr 19, 2010
Messages
2,724
Helped
679
Reputation
1,360
Reaction score
651
Trophy points
1,393
Activity points
19,551
i think you probebly should not write output reg "signal".

Based on the error messages that's indeed a good guess. I just wasn't going to make any assumptions about his program_counter module. :p
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top