Re: verilog query
hi,iam attaching my code here...
the problem is iam not getting the output in ISE simulator.
module buffer(Areal, Breal, Creal, Dreal, addr1,data1, we, clok, addr2,data2,sel);
output [7:0] Areal;
output [7:0] Breal;
output [7:0] Creal;
output [7:0] Dreal;
input [4:0] addr1;
input [31:0] data1;
input we;
input clok;
input [4:0] addr2;
input [31:0] data2;
//input we2;
//input clok2;
input sel;
wire [31:0]A;
wire [7:0]B;
wire [7:0]C;
wire [7:0]D;
wire [7:0]E;
wire [31:0]F;
wire [7:0]G;
wire [7:0]H;
wire [7:0]I;
wire [7:0]J;
//reg Areal,Breal,Creal,Dreal;
ram1 RAM1(A,B,C,D,E,addr1,data1,we,cl0k);
ram2 RAM2(F,G,H,I,J,addr2,data2,we,clok);
mux1 mymux1(Areal,B,E,sel);
mux2 mymux2(Breal,C,F,sel);
mux3 mymux3(Creal,D,G,sel);
mux4 mymux4(Dreal,E,H,sel);
endmodule
regards,
thx.