Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Help me with Verilog code for implementing RAM

Status
Not open for further replies.

neefa

Member level 1
Joined
Sep 13, 2006
Messages
39
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,541
hi frnz,
I need to implement a RAM.which is designed in such a way that it takes 32 bit input with 32 registers and it should give the o/p in 4 parallel sequence 8 bits each In my code iam unable to get this .plzz help...iam attaching my code here.


module ram4(q,q1,q2,q3,q4, d, a, we, clk);
output [31:0] q;
output [7:0] q1;
output [7:0] q2;
output [7:0] q3;
output [7:0] q4;

input [31:0] d;
input [4:0] a;
input we;
input clk;

reg [31:0] read_add;
reg [31:0] mem [31744:0];
//reg [31:0]temp_reg;
always @(posedge clk) begin
if (we)
mem[a] <= d;

read_add <= a;
end

assign q = mem[read_add];
assign q1 = q[7:0];
assign q2 = q[15:8];
assign q3 = q[23:16];
assign q4 = q[31:24];


endmodule
thanks.
 

echo47

Advanced Member level 5
Joined
Apr 7, 2002
Messages
3,942
Helped
637
Reputation
1,272
Reaction score
88
Trophy points
1,328
Location
USA
Activity points
33,183
verilog query

Your code looks ok, except the sizes of 'read_add' (32 bits) and 'mem' (31745 words) are inconsistent with the size of 'a' (5 bits).

What kind of malfunction are you seeing?

The way you control the addresses, the module simply delays the input data by one clock. That's unexciting behavior.
 

nand_gates

Advanced Member level 3
Joined
Jul 19, 2004
Messages
892
Helped
175
Reputation
350
Reaction score
51
Trophy points
1,308
Activity points
6,836
Re: verilog query

I have corrected ur code!

Code:
module ram4(q,q1,q2,q3,q4, d, a, we, clk); 
output [31:0] q; 
output [7:0] q1; 
output [7:0] q2; 
output [7:0] q3; 
output [7:0] q4; 

input [31:0] d; 
input [4:0] a; 
input we; 
input clk; 

reg [31:0] mem [0:31]; 
reg [31:0] q_tmp;
always @(posedge clk) begin 
    q_tmp <= mem[a];
    if (we) 
        mem[a] <= d; 
end 

assign q = q_tmp; 
assign q1 = q_tmp[7:0]; 
assign q2 = q_tmp[15:8]; 
assign q3 = q_tmp[23:16]; 
assign q4 = q_tmp[31:24]; 
endmodule
 

    neefa

    Points: 2
    Helpful Answer Positive Rating

neefa

Member level 1
Joined
Sep 13, 2006
Messages
39
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,541
Re: verilog query

really i thank u for ur help...now my code is running correctly.my next step is to take these 4 outputs and to give to 4,2to 1 mux.for the other o/p to the muxi have to design similar ram.after muxing i will get 4 o/ps.
plz give me suggestions to start my code.
thanks.
 

neefa

Member level 1
Joined
Sep 13, 2006
Messages
39
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,541
Re: verilog query

hi,iam attaching my code here...
the problem is iam not getting the output in ISE simulator.


module buffer(Areal, Breal, Creal, Dreal, addr1,data1, we, clok, addr2,data2,sel);
output [7:0] Areal;
output [7:0] Breal;
output [7:0] Creal;
output [7:0] Dreal;
input [4:0] addr1;
input [31:0] data1;
input we;
input clok;
input [4:0] addr2;
input [31:0] data2;

//input we2;
//input clok2;
input sel;

wire [31:0]A;
wire [7:0]B;
wire [7:0]C;
wire [7:0]D;
wire [7:0]E;
wire [31:0]F;
wire [7:0]G;
wire [7:0]H;
wire [7:0]I;
wire [7:0]J;
//reg Areal,Breal,Creal,Dreal;
ram1 RAM1(A,B,C,D,E,addr1,data1,we,cl0k);
ram2 RAM2(F,G,H,I,J,addr2,data2,we,clok);
mux1 mymux1(Areal,B,E,sel);
mux2 mymux2(Breal,C,F,sel);
mux3 mymux3(Creal,D,G,sel);
mux4 mymux4(Dreal,E,H,sel);
endmodule



regards,
thx.
 

echo47

Advanced Member level 5
Joined
Apr 7, 2002
Messages
3,942
Helped
637
Reputation
1,272
Reaction score
88
Trophy points
1,328
Location
USA
Activity points
33,183
verilog query

Need more info to help you.
Can you show us your testbench, ram1 and ram2, mux1 through mux4, and whatever other modules they may use?
Also, what is your code suppose to do?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top