Hi,
if it is acadamic project then try to build mini library of asic.
Steps you need to follow are below.
1. write verilog code for inverter.
2. simulate your RTL and check functionality.
3. if functinality achived then do synthesis of that and generate netlist.
4. do simulation of your netlist with same testbench and check whether functinality alter or not. if not alter go to step 5 else loop back.
5. inport netlist to yor backend tool and make layout of that.
6. do physical verification like DRC, LVS, etc...
7. try to simulate your layout netlist in spice engine.
8. Study inverter charcteristics.
9. Gnerate GDSII file
10. your first library componant is ready to use.
repeat all these steps for AND, OR, XOR, XNOR, NAND, NOR, Half ADDER/SUBTRACTOR, FULL ADDER/SUBTRACTOR.
I think this will be more helpful for 3 month project.
Let others comment on this.
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Shitansh Vaghela