Help me with Asic project ideas!

[chetya]

Asic project ideas

Hi... I am supposed to do a asic project....(From spec to layout ) in a duration of 3 months... can anybody suggest any project idea which can be done within 3 months.....tools available are xilinx(front end).. cadence(back end)

 

[shitansh]

Re: Asic project ideas

HI,

Suggetion is depends on below question.

Is this acadamic project?
What is pourpose of this project? to learn and get familier with Asic flow?

 

[ljxpjpjljx]

Re: Asic project ideas

which application you prefer?

 

[RaphyDu]

3 months is too short. I guess you can only work out some simple projects like 8-bit MCU, or ALU unit like multiplier(fixed point, floating point), audio encoder/decoder....You actually have quite a few options.

 

[chetya]

Hi all, its an academic project, to get familiar with the asic flow....
Any application is ok....I am actually concerned with complexity... would prefer applications can be implemented in this duration

@RaphyDu....can u elaborate on audio encoder/decoder

 

[shitansh]

Hi,

if it is acadamic project then try to build mini library of asic.

Steps you need to follow are below.

1. write verilog code for inverter.
2. simulate your RTL and check functionality.
3. if functinality achived then do synthesis of that and generate netlist.
4. do simulation of your netlist with same testbench and check whether functinality alter or not. if not alter go to step 5 else loop back.

5. inport netlist to yor backend tool and make layout of that.
6. do physical verification like DRC, LVS, etc...
7. try to simulate your layout netlist in spice engine.
8. Study inverter charcteristics.
9. Gnerate GDSII file
10. your first library componant is ready to use.

repeat all these steps for AND, OR, XOR, XNOR, NAND, NOR, Half ADDER/SUBTRACTOR, FULL ADDER/SUBTRACTOR.

I think this will be more helpful for 3 month project.

Let others comment on this.

--
Shitansh Vaghela

 

[dainvinciblz]

@ shitansh

I really liked your concept
Even 'm worried about doing one such academic project
Hopefully my HOD likes it

Thank you

 

[chetya]

Hi shitansh,
Thanks for sending an elaborate reply . A std library already exists and we are supposed to implement some functional block like FIR fiilter etc using the lib.... I am in search for such ideas that could be implemented......

 

[shitansh]

Hi shitansh,
A std library already exists

Its always ready and rarely you need to buid standard cell library. Basic idea of this exercise are
1. you will be familier with ASIC flow. will know full RTL to GDS process
2. Once you learn inverter in digital then all are same.
3. Will come to know effect of lay out on performance...etc...

we are supposed to implement some functional block like FIR fiilter etc using the lib.... I am in search for such ideas that could be implemented......

Any way all this kind of stuff you are going to do in your job period then why not to make base clear instead of doing this kind of stuff now?

--
Shitansh Vaghela

 

[upender]

Hi shitansh,

I really liked your flow...

Thank you.

 

[madhunandyala]

Hello Shitansh,

I am Madhu N, i am also planning to do a small academic project as u all said above. I have only Tanner tool that will not support coding and all the remaining things. Would u please tell me a free or cracked tool which does from RTL to GDSII? Please help me boss!!!!!!!!!!!!!!!!waiting for your reply.....