Help me with a VHDL code for counter in a parallel to serial block

[a_fetoh]

Hello,
there is a Parallel to serial block in my system which i make it with a 64*1 mux and 6-bit counter .
I want the counter to stop when it reach "111111" and start again from "000000" when the input changed.

I've tried many methods, something like that :

process (data_in)
begin
if x2="111111" then --o/p of counter
x3<='1';
else
x3<='0';
end if;
end process;

where x2 is the output of the counter and x3 is a signal when it equals 1 the counter restart from "000000"
But the prolblem is when the counter eraches "111111", x3 remains 1 and i want it changed to 1 for only a period of one clock.

Does any1 have suggestions ?
Thanks,

 

[omara007]

help in a VHDL code

Try to change your code to this :

if x2 <= "111111" then
x3 <= '1';

 

[calm]

help in a VHDL code

i think

if x2 <= "00000" then
x3 <= '1';

 

[omara007]

Re: help in a VHDL code

i think

if x2 <= "00000" then
x3 <= '1';

the problem is not in the number he is checking .. the problem is that his condition only valies when x2 is equal to a certain number .. otherwise, x3 won't be equal to '1' .. while he should make the condition as , if x2 if smaller than or equal to "whatever" ..

 

[a_fetoh]

help in a VHDL code

i'm trying another solution but it is long, if it going well, i'll inform you

 

[nand_gates]

Re: help in a VHDL code

Hello,
there is a Parallel to serial block in my system which i make it with a 64*1 mux and 6-bit counter .
I want the counter to stop when it reach "111111" and start again from "000000" when the input changed.

I've tried many methods, something like that :

process (data_in)
begin
if x2="111111" then --o/p of counter
x3<='1';
else
x3<='0';
end if;
end process;

where x2 is the output of the counter and x3 is a signal when it equals 1 the counter restart from "000000"
But the prolblem is when the counter eraches "111111", x3 remains 1 and i want it changed to 1 for only a period of one clock.

Does any1 have suggestions ?
Thanks,

Your requirement looks very starange! I think what you need is a data_valid signal
which goes high when new data arrives.
Check out this code!
Hope this helps!

process (clk, reset_n)
begin
if reset_n = '0' then
   x2 <= (others => '1')
elsif clk'event and clk = '1' then  --o/p of counter
   if x2="111111" then
      x2 <= not data_valid & not data_valid & not data_valid & not data_valid & not data_valid & not data_valid;
   else
      x2 <= x2 + 1;
   end if;  
end if;
end process;

 

[salma ali bakr]

Re: help in a VHDL code

if x3 remains '1'...then this means that the counter x2 is always at "111111"..
are you sure that the signal x3 is used in another process to reset the counter...!

or it also means that there isn't any new data that comes in....and the execution doesn't go into the process at all...

 

[keerthiraj]

Re: help in a VHDL code

use two more signals like a,b. and use xor2 userdefined component

uuuuuu : xor2 port map (a,b,x3);
process (data_in)
begin
if x2="111111" then --o/p of counter
x<='1';
else
y<='1 --take two variables x,y';
end if;
end process;
a<=x;
b<=y;

i think this code vil help u....