Follow along with the video below to see how to install our site as a web app on your home screen.
Note: This feature may not be available in some browsers.
if reset = '1' then
Si <= (others => '0');
elsif rising_edge(clk) then
Si <= Si + Xi;
end if;
if u r writing in verilog then
CODE:
always @ (posedge clk or posedge reset)
if (reset==1)
si=xi;
else
si=si+xi;
Any reason to assume, that the synthesis tool is not inferring a carry-look ahead adder?here i am not using normal addition the addition module is carry look ahead adder
if want to make sure thats carry lookahead adder, may consider to design the carrylookahead adder in a new module with FULL STRUCTURAL (design using AND,OR,XOR gates).
typically need to use some generate i to Si_Size code to generate your Full Adder and connect the worst case propagation delay path to some AND gate or OR gate to ur SUM and CARRY.
Carrylookahead model can easily find in google as well.
process(clk)
begin
if (clk'event and clk = '1') then
C <= A + Register;
Register <= C;
end if;
end process
if u r writing in verilog then
CODE:
always @ (posedge clk or posedge reset)
if (reset==1)
si=xi;
else
si=si+xi;