help me to write code for following circuit

[harinisas]

in this circuit the adder is a carry look ahead adder

 

[FvM]

E.g.:

if reset = '1' then
  Si <= (others => '0');
elsif rising_edge(clk) then
  Si <= Si + Xi;
end if;

 

[rknmahesh]

if u r writing in verilog then

CODE:
always @ (posedge clk or posedge reset)
if (reset==1)
si=xi;
else
si=si+xi;

 

[harinisas]

if u r writing in verilog then

CODE:
always @ (posedge clk or posedge reset)
if (reset==1)
si=xi;
else
si=si+xi;

here i am not using normal addition the addition module is carry look ahead adder

 

[rknmahesh]

Better know what a carry look ahead do. it calculates carry in advance. U have shown only the sum in the module.
u chech again ur question

 

[FvM]

here i am not using normal addition the addition module is carry look ahead adder

Any reason to assume, that the synthesis tool is not inferring a carry-look ahead adder?

 

[TuAtAu]

if want to make sure thats carry lookahead adder, may consider to design the carrylookahead adder in a new module with FULL STRUCTURAL (design using AND,OR,XOR gates).

typically need to use some generate i to Si_Size code to generate your Full Adder and connect the worst case propagation delay path to some AND gate or OR gate to ur SUM and CARRY.

Carrylookahead model can easily find in google as well.

 

[harinisas]

if want to make sure thats carry lookahead adder, may consider to design the carrylookahead adder in a new module with FULL STRUCTURAL (design using AND,OR,XOR gates).

typically need to use some generate i to Si_Size code to generate your Full Adder and connect the worst case propagation delay path to some AND gate or OR gate to ur SUM and CARRY.

Carrylookahead model can easily find in google as well.

i have already implemented carry look ahead adder in structural model but when i am giving a feed back loop with register its not taking the previous value

 

[TuAtAu]

you want it to take the previous value, make sure u done correct in the clock timing description..

such as:

process(clk)
begin
 if (clk'event and clk = '1') then
    C <= A + Register;
    Register <= C;
 end if;
end process

Then you will have feedback effect.

 

[syedshan]

if u r writing in verilog then

CODE:
always @ (posedge clk or posedge reset)
if (reset==1)
si=xi;
else
si=si+xi;

always use non-blocking statement when using posedge clock...
i.e. su <= xi;