if want to make sure thats carry lookahead adder, may consider to design the carrylookahead adder in a new module with FULL STRUCTURAL (design using AND,OR,XOR gates).
typically need to use some generate i to Si_Size code to generate your Full Adder and connect the worst case propagation delay path to some AND gate or OR gate to ur SUM and CARRY.
Carrylookahead model can easily find in google as well.
if want to make sure thats carry lookahead adder, may consider to design the carrylookahead adder in a new module with FULL STRUCTURAL (design using AND,OR,XOR gates).
typically need to use some generate i to Si_Size code to generate your Full Adder and connect the worst case propagation delay path to some AND gate or OR gate to ur SUM and CARRY.
Carrylookahead model can easily find in google as well.
i have already implemented carry look ahead adder in structural model but when i am giving a feed back loop with register its not taking the previous value