I am sorry, but I still don't understand your sentence: "and the higher peak voltage is 1.92V, which is the operating point".
Regarding the AC voltage in B due to V1
Imagine that from B to ground (or VDD) there is 1 pF capacitance (see it as fet capacitances, modelled as C1 in the imgage).
So we have a series circuit of C1 (20pF) and 1pF to ground. However from B to ground there is also the output impedance of the current mirror (P2) and N1, all modelled as R1). There is also a controlled current source (N1's transconductance, modelled as G1). `
For low frequency, the behavior is dominated by N1's transconductance and R1 (as you can ignore the capacitances).
At very high frequency, X(C1) << R1, and X(C1) << 1/G(n1), so R1 and 1/G can be ignored. In other words, all current flowing into C1 goes through C2 and a capacitive voltage divider has been created. X(..) = reactance of.
Vb = V1(10p/(10p+1p) ) = 0.91*V1.
So if V1 = 10 mVp, Vb = 9.1mVp (that is 18.2mVpp). This AC voltage is centered around the DC bias voltage in B (ignoring non-linearity of the fet characteristics). If the fet capacitances are less (so C1 has lower value), voltage in B will increase to maximum 20mVpp.