Help me solve this DRV violations

[vlsitechnology]

Inst pin Max cap cap cap slk remark
DIR_BE_Q 0.175 4.438 -4.263 E
PIF_TIF_ACK_X 0.175 4.438 -4.263 E
USB_GNT_IN_N 0.175 4.438 -4.263 E


Can anyone tell me how to fix this max cap violations i am getting 33 violations and max fanout violations are 94 as........

Inst pin max fanload fanload fanslk cell port remark
clk150_temp2_l2_i32 16 65 -49 clkbd32/z C
clk66_temp2_l2_i18/z 16 63 -47 clkbd32/z C
clk150_temp2_l2_i8/z 16 63 -44 clkbd32/z C
usb_clk_in_temp2_l2_i14/z 16 65 -49 clkbd32/z C

Bye take care

 

[iwpia50s]

Total DRV violations

Looks like these are in the clock trees and your cts tool did not do a good job. What did you specify in your cts constraints?

 

[vlsitechnology]

Total DRV violations

Hello iwpia

I have given clock buffers and inverters in the clock tree specification file and thn saved it and we have done from the gui mode
Bye tke care

Added after 3 minutes:

I mean footprints we gave an input to clk tree specification file and clockDesign command for synthesis bcz it was giving errors when i used the option from the gui mode donno why.....
Bye take care