Hi,
pls help me out from this thing is that i generate BRAM using coregen with .cof file also and when i try to simulate the Design in model sim then error is coming like fail to open vhdl file ram_block.mif(memory initianilize file) in rb mode.Why is it so???????
I am in big trouble,pls reply...
Looks like you are using 'ROM" in your design and try to simulate it.
If you can open the primitive, you can find one generic which points to the "mif" file. For simulation, you must put the mif file to the correct dir.