Dinesh Lohan
Newbie level 4

Hi,
pls help me out from this thing is that i generate BRAM using coregen with .cof file also and when i try to simulate the Design in model sim then error is coming like fail to open vhdl file ram_block.mif(memory initianilize file) in rb mode.Why is it so???????
I am in big trouble,pls reply...
Dinesh
IIT,Delhi
pls help me out from this thing is that i generate BRAM using coregen with .cof file also and when i try to simulate the Design in model sim then error is coming like fail to open vhdl file ram_block.mif(memory initianilize file) in rb mode.Why is it so???????
I am in big trouble,pls reply...
Dinesh
IIT,Delhi