Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Help me solve an issue in VHDL code writing

Status
Not open for further replies.

555lin

Junior Member level 3
Joined
Aug 19, 2005
Messages
26
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,638
Guys I can't solve the problem of writing VHDL code, that
implies executing an intialization part that is to be executed only once and
the other part is to be regularly repeated and both parts(init and work) have
the same signals.
How can I solve it?
 

Joined
Sep 3, 2007
Messages
853
Helped
66
Reputation
132
Reaction score
16
Trophy points
1,298
Activity points
0
VHDL code question

Hi,
Try ti design the state machine. There is nice materiasl on FSM in edaboard.
Hope it help !
 

avimit

Banned
Joined
Nov 16, 2005
Messages
413
Helped
91
Reputation
182
Reaction score
23
Trophy points
1,298
Location
Fleet, UK
Activity points
0
Re: VHDL code question

Well pls elaborate. if you are writing a testbench, then you can init a signal while declaring it, for example:
signal mysignal : std_logic := '0';
This will make sure that mysignal gets a value of '0' at start and then you can assign any value to it in your code.
Hope it helps,
Kr,
Avi
http://www.vlsiip.com
 

lordsathish

Full Member level 5
Joined
Feb 11, 2006
Messages
247
Helped
33
Reputation
66
Reaction score
3
Trophy points
1,298
Location
Asia
Activity points
2,698
Re: VHDL code question

If you are not writing a test bench then you could well use a reset or preset signal in case of flip flops in your design else you can use an enable signal for combinational elements....
 

hjavadi

Newbie level 5
Joined
Oct 31, 2005
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,342
Re: VHDL code question

You can use EN (enable signal) in your design.
 

salma ali bakr

Advanced Member level 3
Joined
Jan 27, 2006
Messages
971
Helped
104
Reputation
206
Reaction score
21
Trophy points
1,298
Activity points
7,491
Re: VHDL code question

you can have an enable signal with an if else statement, that will have the initial part after the if enable and the work part after the else...
or just the "initial" part written then a loop for the "work" part..
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top