Help me solve an issue in VHDL code writing

[555lin]

Guys I can't solve the problem of writing VHDL code, that
implies executing an intialization part that is to be executed only once and
the other part is to be regularly repeated and both parts(init and work) have
the same signals.
How can I solve it?

 

[master_picengineer]

VHDL code question

Hi,
Try ti design the state machine. There is nice materiasl on FSM in edaboard.
Hope it help !

 

[avimit]

Re: VHDL code question

Well pls elaborate. if you are writing a testbench, then you can init a signal while declaring it, for example:
signal mysignal : std_logic := '0';
This will make sure that mysignal gets a value of '0' at start and then you can assign any value to it in your code.
Hope it helps,
Kr,
Avi
http://www.vlsiip.com

 

[lordsathish]

Re: VHDL code question

If you are not writing a test bench then you could well use a reset or preset signal in case of flip flops in your design else you can use an enable signal for combinational elements....

 

[hjavadi]

Re: VHDL code question

You can use EN (enable signal) in your design.

 

[salma ali bakr]

Re: VHDL code question

you can have an enable signal with an if else statement, that will have the initial part after the if enable and the work part after the else...
or just the "initial" part written then a loop for the "work" part..