Help me solve a task about memory description in VHDL

[RS6688]

a question

Hi,

Who can help me answer this question?I will appreciate you.Thank you.

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For the VHDL memory description, the following inputs occur:
For clk1 cycles, N, N+1, N+2, N+3, N+4:
WE1 is 1 on N, N+1
ADD1 is A0 on N, A1 on N+1, A1 on N+2, A0 on N+3
DI1 is D0 on N, D1 on N+1

WE2 is 1 on N+1, N+2
ADD1 is A0 on N+1, A1 on N+2, A1 on N+3, A0 on N+4
DI2 is D2 on N+1, D3 on N+2

a. What is DO1 for N through N+4?
b. What is DO2 for N through N+5?

entity raminfr is
port ( clk1 : in std_ logic;
we1, we2 : in std_logic;
add1, add2 : in std_logic;
di1, di2 : in std_logic_vector(3 downto 0);
do1, do2 : out std_logic_vector(3 downto 0)
end entity;

architecture syn of raminfr is
type ram_type is array (31 downto 0) of std_ logic_ vector (3 downto 0);
signal RAM : ram_type;
signal read_add1 : std_ logic_ vector( 4 downto 0);
signal read_add2 : std_ logic_ vector( 4 downto 0);
begin

process (clk1)
begin
if (clk1’event and clk1 = ’1’) then
if (we = ’1’) then
RAM( conv_ integer( add1)) <= di1;
end if;
read_add1 <= add1;
end if;
end process;

do1 <= RAM( conv_ integer( read_ add1));

process (clk1)
begin
if (clk1’event and clk1 = ’1’) then
if (we2 = ’1’) then
RAM( conv_ integer( add2)) <= di2;
end if;
read_ add2 <= add2;
end if;
end process;

do2 <= RAM( conv_ integer( read_ add2));
end syn;

 

[cube007]

a question

Hello RS6688,

Do you need this information because you have to do it for your teacher or for learning VHDL by yourself? The best way to get the answer is to use a simulation program like ModelSim or something else. You can also get a free version of Altera Quartus II or Xilinx from the Web to do some simulations. You will learn a lot with these tools.


Bye,
cube007

 

[masai_mara]

Re: a question

hi,
As per your code, it would go like this:-
N N+1 N+2 N+3 N+4
do1 ?? DO D1 ?? ??
do2 ?? ?? D2 D3 ??

this is because we dont know what values are stored in the other addresses.

but the best way is to simulate it.