help me plz..am doing a project in verilog..i hav enclosed my prg below...

[savithaarumughan]

here i want to find the sum of 36 mem values and hv to find log2 of that sum value.... also i have to defir the window size as 36.. hw to do this.. can u help me.....
plz...

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Code Verilog - [expand]
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module pi(sin,dpcm,k,sum,clk,reset);
input clk,reset;
output reg[7:0]sin;
output reg[7:0]dpcm;
reg [5:0]count;
reg [5:0]i;
reg tot,t;
output reg k;
output reg [8:0]sum;
 
 
reg [7:0]mem[36:0];
always @(posedge clk or posedge reset)
 
begin
if(reset)
     begin
count=6'b000000;
sin=8'b00000000;
i=6'b000000;
t=6'b000000;
 
      end 
else
    begin
mem[0]=8'b00000000;
mem[1]=8'b00001100;
mem[2]=8'b00011001;
mem[3]=8'b00001100;
mem[4]=8'b00000000;
mem[5]=8'b00000000;
mem[6]=8'b00000000;
mem[7]=8'b00000000;
mem[8]=8'b11111110;
mem[9]=8'b11111011;
mem[10]=8'b00000000;
mem[11]=8'b01100000;
mem[12]=8'b00000000;
mem[13]=8'b11110001;
mem[14]=8'b11100010;
mem[15]=8'b11110001;
mem[16]=8'b00000000;
mem[17]=8'b00000000;
mem[18]=8'b00000000;
mem[19]=8'b00000000;
mem[20]=8'b00000000;
mem[21]=8'b00000001;
mem[22]=8'b00000011;
mem[23]=8'b00000110;
mem[24]=8'b00001100;
mem[25]=8'b00011001;
mem[26]=8'b00110010;
mem[27]=8'b00011001;
mem[28]=8'b00000000;
mem[29]=8'b00000000;
mem[30]=8'b00000000;
mem[31]=8'b00000001;
mem[32]=8'b00000100;
mem[33]=8'b00001001;
mem[34]=8'b00000100;
mem[35]=8'b00000000;
mem[36]=8'b00000000;
sin=mem[count];
count=count+1; 
    dpcm[0]=mem[0];
                dpcm=mem[i]-mem[i-1];

---

 

[nisshith]

first problem with this code is that output must of 43 bits. sum of 36 8-bits number cannot be a 8-bit number

 

[nisshith]

what is purpose of each output/input pin ?
the logic u can use to get the real part of log(base2) could be to search for '1' starting from MSB of the generated sum.
and the position for first '1' from MSB is the real part for log.
For example if number is 0110001 first '1' from left side is at 5th position.
Therefore, LOG2(0110001)=5.{some fractional value}
to get the fractional value you have to think of something else. But as far as real part is concerned this algorithm will work fine.
I can write the program for that but you have to tell me the purpose of each o/p and i/p pin, and also the working of whole hardware (Problem statement)

 

[savithaarumughan]

what is purpose of each output/input pin ?
the logic u can use to get the real part of log(base2) could be to search for '1' starting from MSB of the generated sum.
and the position for first '1' from MSB is the real part for log.
For example if number is 0110001 first '1' from left side is at 5th position.
Therefore, LOG2(0110001)=5.{some fractional value}
to get the fractional value you have to think of something else. But as far as real part is concerned this algorithm will work fine.
I can write the program for that but you have to tell me the purpose of each o/p and i/p pin, and also the working of whole hardware (Problem statement)

Hello sir... thanks for ur reply... my project is compression of signal using golomb rice coding..here we have manually generated one wave .. each mem values represents the amplitute values.. output pin k is the coding parameter of golomb code.. to do this golomb code i have to find the k parameter..the formula for k is K=LOG2(SUM/WS).... sum is the addition of all 36 mem values.. and ws is default vaalue 36...and also i request u to tell some ideas to find out the log base 2 values as soon as possible sir...

 

[amberyn]

here i want to find the sum of 36 mem values and hv to find log2 of that sum value.... also i have to defir the window size as 36.. hw to do this.. can u help me.....
plz...

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Code Verilog - [expand]
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module pi(sin,dpcm,k,sum,clk,reset);
input clk,reset;
output reg[7:0]sin;
output reg[7:0]dpcm;
reg [5:0]count;
reg [5:0]i;
reg tot,t;
output reg k;
output reg [8:0]sum;
 
 
reg [7:0]mem[36:0];
always @(posedge clk or posedge reset)
 
begin
if(reset)
     begin
count=6'b000000;
sin=8'b00000000;
i=6'b000000;
t=6'b000000;
 
      end 
else
    begin
mem[0]=8'b00000000;
mem[1]=8'b00001100;
mem[2]=8'b00011001;
mem[3]=8'b00001100;
mem[4]=8'b00000000;
mem[5]=8'b00000000;
mem[6]=8'b00000000;
mem[7]=8'b00000000;
mem[8]=8'b11111110;
mem[9]=8'b11111011;
mem[10]=8'b00000000;
mem[11]=8'b01100000;
mem[12]=8'b00000000;
mem[13]=8'b11110001;
mem[14]=8'b11100010;
mem[15]=8'b11110001;
mem[16]=8'b00000000;
mem[17]=8'b00000000;
mem[18]=8'b00000000;
mem[19]=8'b00000000;
mem[20]=8'b00000000;
mem[21]=8'b00000001;
mem[22]=8'b00000011;
mem[23]=8'b00000110;
mem[24]=8'b00001100;
mem[25]=8'b00011001;
mem[26]=8'b00110010;
mem[27]=8'b00011001;
mem[28]=8'b00000000;
mem[29]=8'b00000000;
mem[30]=8'b00000000;
mem[31]=8'b00000001;
mem[32]=8'b00000100;
mem[33]=8'b00001001;
mem[34]=8'b00000100;
mem[35]=8'b00000000;
mem[36]=8'b00000000;
sin=mem[count];
count=count+1; 
    dpcm[0]=mem[0];
                dpcm=mem[i]-mem[i-1];

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as i know, verilog 1364-2001 IEEE just support combined data type (mem[]) with constant (mem[1]), but not virable (mem)

 

[pprv]

cud u plz give me d correct code for golomb rice encoding...