agobgocgo
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This is my first time using VHDL but I can't understand how can I make the testbench for these.. please let me know testbench for these.
module adder1(a,b,cin,cout,s);
parameter n=8;
input [n-1:0] a,b;
input cin;
output [n-1:0] s;
output cout;
assign {cout,s}=a+b+cin;
endmodule
module adder2(a,b,cin,cout,s);
parameter n=8;
input [n-1:0] a,b;
input cin;
output [n-1:0] s;
output cout;
wire [n-1:0] p= a^b;
wire [n-1:0] g= a&b;
wire [n:0] c={g|(p&c[n-1:0]), cin};
assign s=p^c[n-1:0];
assign cout =c[n];
endmodule
module adder1(a,b,cin,cout,s);
parameter n=8;
input [n-1:0] a,b;
input cin;
output [n-1:0] s;
output cout;
assign {cout,s}=a+b+cin;
endmodule
module adder2(a,b,cin,cout,s);
parameter n=8;
input [n-1:0] a,b;
input cin;
output [n-1:0] s;
output cout;
wire [n-1:0] p= a^b;
wire [n-1:0] g= a&b;
wire [n:0] c={g|(p&c[n-1:0]), cin};
assign s=p^c[n-1:0];
assign cout =c[n];
endmodule