help me optimize this VHDL to verilog conversion

[raghava216]

Hi..

I want to know the best way of converting the below VHDL code to verilog code

First type of VHDL code:

---

Code VHDL - [expand]
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a0_n <= a_i(0)  WHEN d_en_i = '1' AND
               dat_en_i= '1' ELSE
               '1' WHEN d_en_i = '1' ELSE
               'Z';

---

There are two ways I can think of writing this code in verilog.

1)

assign a0_n = (d_en_i == 1'b1 && dat_en_i == 1'b1) ? a_i[0] : (d_en_i == 1'b1 ? 1'b1 : 1'bZ);

2)

---

Code Verilog - [expand]
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always @ (*)
begin
    if(d_en_i == 1'b1 && dat_en_i == 1'b1)
        a0_n = a_i[0];
    else if (d_en_i == 1'b1)
        a0_n = 1'b1;
    else
        a0_n = 1'bZ;
end

---

Second type of VHDL code:

---

Code VHDL - [expand]
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d <= d_i WHEN rd_en1_i = '1' AND dat_en_i= '1' ELSE
         dc1  WHEN (rd_en2_i='1'  AND dat_en_i= '1')OR
                         ld_en = '1' ELSE
         d1        WHEN (in_n_i = '0' OR (int_i = '0'      AND
                       pro_i = '1' AND tran_i = '1'))   ELSE
         "ZZZZZZZZ";

---

1)

---

Code Verilog - [expand]
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always @(*)
begin
if(rd_en1_i == 1'b1 && dat_en_i == 1'b1)
d = d_i;
else if ((rd_en2_i == 1'b1 && dat_en_i == 1'b1) || (ld_en == 1'b1))
d = dc1;
else if ((in_n_i = 1'b0 ||(int_i == 1'b0 && pro_i == 1'b1 && tran_i == 1'b1))
d = d1;
else
d = 8'bZ;
end

---

2)

---

Code Verilog - [expand]
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assign d = (rd_en1_i == 1'b1 && dat_en_i == 1'b1) ? d_i : (((rd_en2_i == 1'b1 && dat_en_i == 1'b1) || (ld_en == 1'b1))) ? dc1 : (((in_n_i = 1'b0 ||(int_i == 1'b0 && pro_i == 1'b1 && tran_i == 1'b1))) ? d1 : 8'bZ;

---

Now, For this code, writing in an always block is better or writing as conditional statement is better (in verilog) ? or both are equivalent?

What are the implications of these 2 versions?
Which one is to be used when? and Which is more optimum? I think their synthesis results are the same.

 

[rca]

what are the goal to convert a code from one language to other one?

 

[raghava216]

@rca

I work with both the HDLs.
I am interested to know the equivalents in both to improve my understanding.

 

[FvM]

Presumed both codes are functionally equivalent (they look like at first sight), then the decision is just a matter of taste or style. Readability would be my personal priority.

In both second examples, you changed concurrent code into sequential. It has no immediate implications in the present case, but literally it's a different kind of behavioral description. You could choose sequential code in VHDL as well, but you didn't for some reason.

what are the goal to convert a code from one language to other one?

Most synthesis tools understand both languages and have no problem with mixed language designs. Modelsim however needs an separate license for it (at extra charge), the free vendor editions don't include it. This can be a trivial but plausible reason to translate some design modules.

Finally, some customers don't like one or the other language. They possibly ask you for their convenience to translate delivered code.

 

[raghava216]

@FvM

Thanks for ur reply.

You are right in saying that

I changed concurrent code into sequential in both the second examples

.
But, in the always block, there is only a single if-else, so I guess it won't effect much if its concurrent or sequential.
May be that is why you said

it has no immediate implications in the present case

. But I did not get how it would mean different kinds of behavioral description.

You could choose sequential code in VHDL as well, but you didn't for some reason.

That is the code I want to convert. I cannot change it.

Most synthesis tools understand both languages and have no problem with mixed language designs. Modelsim however needs an separate license for it (at extra charge), the free vendor editions don't include it. This can be a trivial but plausible reason to translate some design modules.

Finally, some customers don't like one or the other language. They possibly ask you for their convenience to translate delivered code

Yes, it is often the requirement of customers/foundries to choose one HDL over other.

 

[FvM]

But I did not get how it would mean different kinds of behavioral description.

That's a pure formal point. Different chapters in the language specification, different syntax, different scheduling rules.