Look at the pic here. A is the non-reversed input port, B is reversed input. All the transistors are PMOS and Idc is the bias current for amp6. Theredically, the voltage of A should equal with B.but the simulation results show that if P3 is on, VB quickly reaches approximately VDD.And the voltage of node C finally attends to a very low potential.
Please tell what's wrong with this ckt?
Look at the pic here. A is the non-reversed input port, B is reversed input. All the transistors are PMOS and Idc is the bias current for amp6. Theredically, the voltage of A should equal with B.but the simulation results show that if P3 is on, VB quickly reaches approximately VDD.And the voltage of node C finally attends to a very low potential.
Please tell what's wrong with this ckt?
Thank you for your replies.
the A is the input signal , the gate voltage should be determined by A. And as I imagine the current through P3,P4 will be variable while VA is changing.
Additionally, the drain of P2 and P5 is floating.