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help me on this problem!!

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eda_range

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Look at the pic here. A is the non-reversed input port, B is reversed input. All the transistors are PMOS and Idc is the bias current for amp6. Theredically, the voltage of A should equal with B.but the simulation results show that if P3 is on, VB quickly reaches approximately VDD.And the voltage of node C finally attends to a very low potential.
Please tell what's wrong with this ckt?

Thank you!
 

eda_range

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Anyone please kindly give me a clue, thank you.
 

northeast1

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eda_range said:
Look at the pic here. A is the non-reversed input port, B is reversed input. All the transistors are PMOS and Idc is the bias current for amp6. Theredically, the voltage of A should equal with B.but the simulation results show that if P3 is on, VB quickly reaches approximately VDD.And the voltage of node C finally attends to a very low potential.
Please tell what's wrong with this ckt?

Thank you!

Hi,
you should exchange A and B terminal. and try

Best regards
Ben
 

eda_range

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I have the same result after change A and B terminal...
 

rainman.cn

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how can you determine the gate voltage of p1,3,6, ?
 

eda_range

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Thank you for your replies.
the A is the input signal , the gate voltage should be determined by A. And as I imagine the current through P3,P4 will be variable while VA is changing.
Additionally, the drain of P2 and P5 is floating.
 

rainman.cn

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you take no effort to stabilize the quiescent point of the ckt, i think. you should add a valid dc neg feedback.
 

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