n.mehr
Newbie level 6
hello
i Receive this errors
please help me
This is very urgent
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(50): Cannot resolve indexed name as type std.standard.bit_vector.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(69): Cannot resolve indexed name as type std.standard.bit_vector.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(90): Illegal target for signal assignment.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(90): Prefix of indexed name must be an array.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(109): Illegal target for signal assignment.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(109): Prefix of indexed name must be an array.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(11): Nonresolved signal 'd_out' has multiple sources.
and this is my code
please help me
i Receive this errors
please help me
This is very urgent
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(50): Cannot resolve indexed name as type std.standard.bit_vector.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(69): Cannot resolve indexed name as type std.standard.bit_vector.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(90): Illegal target for signal assignment.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(90): Prefix of indexed name must be an array.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(109): Illegal target for signal assignment.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(109): Prefix of indexed name must be an array.
** Error: D:/Nasha/VHDL/tamrinat in terme khodemon/dual_buffer/dualbuffer.vhd(11): Nonresolved signal 'd_out' has multiple sources.
and this is my code
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity DualBuffer is
port(d_in : in bit_vector(0 to 7);
d_out: out bit_vector(0 to 7);
wr_addr:inout std_logic;
rd_addr:inout std_logic;
wr_clk :inout std_logic;
rd_clk :inout std_logic);
end entity ;
architecture struct of DualBuffer is
signal empty,full :bit;
signal counter1,counter2 : integer:=0;
signal flag : bit:='1';
signal wr_en1:std_logic;
signal wr_en2:std_logic;
signal rd_en1:std_logic;
signal rd_en2:std_logic;
component Ram is
port( d_in :in bit_vector (0 to 7);
d_out :out bit_vector(0 to 7);
wr_clk,rd_clk :inout std_logic ;
wr_en,rd_en:inout std_logic;
wr_addr:inout std_logic;
rd_addr :inout std_logic);
end component Ram;
begin
Ram1 : component Ram
port map (d_in =>d_in,d_out=>d_out,wr_en=>wr_en1,rd_en=>rd_en1,wr_addr=>wr_addr,rd_addr=>rd_addr,wr_clk=>wr_clk,rd_clk=>rd_clk);
Ram2 :component Ram
port map (d_in =>d_in ,d_out=>d_out,wr_en=>wr_en2,rd_en=>rd_en2,wr_addr=>wr_addr,rd_addr=>rd_addr,wr_clk=>wr_clk,rd_clk=>rd_clk);
write_read : process is
begin
if (rd_clk'event and rd_clk='1' and rd_en1='1') then
if (wr_en1='0') then
if (counter1 /=0) then
d_out <= Ram1(conv_integer(rd_addr));
counter1<= counter1 -1;
flag <='0';
else --Ram1 is empty
wr_en1 <='1';
wait for 10 ns;
rd_en1<= '0';
wait for 10 ns;
wr_en2 <='0';
wait for 10 ns;
rd_en2<='1';
wait for 10 ns;
counter1 <=0;
end if;
end if;
elsif (rd_clk'event and rd_clk='1' and rd_en2='1') then
if(wr_en2='0') then
if(counter2 /=0)then
if (flag /='1')then
d_out<=Ram2(conv_integer(rd_addr));
counter2<= counter2 -1;
else --Ram2 is empty
rd_en2<= '0';
wait for 10 ns;
wr_en2<= '1';
wait for 10 ns;
wr_en1<= '0';
wait for 10 ns;
rd_en1<= '1';
wait for 10 ns;
counter2 <=0;
end if;
end if;
end if;
end if;
if(wr_clk'event and wr_clk='1' and wr_en1='1')then
if(rd_en1='0')then
if(counter1 /=16) then
Ram1(conv_integer(wr_addr))<= d_in;
counter1<=counter1+1;
else --Ram1 is full
wr_en1 <='0';
wait for 10 ns;
rd_en1<='1';
wait for 10 ns;
wr_en2<='1';
wait for 10 ns;
rd_en2<='0';
wait for 10 ns;
counter1<=16;
wait for 10 ns;
end if;
end if;
elsif(wr_clk'event and wr_clk='1' and wr_en2='1')then
if(rd_en2='0')then
if(counter2 /=16)then
Ram2(conv_integer(wr_addr))<=d_in;
counter2<=counter2+1;
else --Ram2 is full
wr_en2 <='0';
wait for 10 ns;
rd_en2 <='1';
wait for 10 ns;
wr_en1 <='1';
wait for 10 ns;
rd_en1 <='0';
wait for 10 ns;
counter2<=16;
wait for 10 ns;
end if;
end if;
end if;
wait on wr_clk,wr_en1,rd_en1,counter1,wr_en2,rd_en2,counter2;
end process ;
fullempty:process is
begin
if(rd_en2='1' and wr_en1='1')then
if(counter1=16 and counter2 /=0) then
full<='1';
end if;
elsif(rd_en1='1' and wr_en2='1')then
if(counter1 /=0 and counter2=16)then
full<='1';
end if;
elsif (rd_en2='1' and wr_en1='1' )then
if( counter1 /=16 and counter2=0) then
empty<= '1';
end if;
elsif(rd_en1='1' and wr_en2 ='1') then
if(counter1=0 and counter2 /=16) then
empty <='1';
end if;
end if;
wait ;
end process fullempty;
end architecture;
configuration conection of DualBuffer is
for struct
for Ram1,Ram2:Ram
use entity work.Dual_Port_Ram(behavior);
end for;
end for ;
end configuration conection ;