i was trying to design one unity gain buffer. below are the specification
unity gain
MOS transistor
TSMC 0.35µm
can anyone help me give some ideas on this unity gain circuit design? it's better to have jus around 6 MOS transistors. i'm using this unity gain in my sample and hold circuit. thank you.
I think minimum OTA consists of 5 transistors for either PMOS load or NMOS load.
Self-biased OP-AMP should consist of 6 transistors.
However, do u need rail-to-rail input?
if yes, it's another story and you cannot achieve that.
if let's say i'm using simple OTA, there is an I Bias. what should i do when i design it? just replace a current source? or is there any way to replace the current source?
Added after 19 minutes:
if i was design my unity gain buffer using OP-amp, can anyone recommend me or show me the internal circuit of op-amp for unity gain buffer?