ASICK
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Hi,
I am a beginner to analog IC.I have read some theory but when it comes to simulation, I just get lost, even at the DC biasing stage. I am trying to design a simple (miller) opamp, which will give me a gain of like 200(either one or 2 stages), i am not worried about the freq response or comp. all I want is a diff amp with this gain a good input and output CM range . I am using cadence TSMC .25u tech. Vdd=2.5V Vss=0, two Pmos load on the top, two diff Nmos below it and nmos current mirror at the bottom. tail current 20u, so current in each arm 10u. I wanted to have like Vod=.4, I calculate all the W/l's for this much current and overdrive, but I cannot seem to control the drain voltages. how do you figure out the drain voltages? from my calculation which seem right on paper, but on cadence get one or other in linear or reverse. and I am not even sure if I have the right values of Kn,Kp and Vth's (109.7uV/AA, -25.5uV/AA, Vthp=-.53, Vth,n=.495V) what am I doing wrong? how do you ideally start the design process?? (I have attached a hand made ckt file also, Pls dont laugh at the drawing)
Can someone guide me in details as how to bias and calculate W/L, what controls the drain voltages, and stuff)? I would really appreciate it. I try each time and give up frustrated...(hope its the right place to post this) let me know if you need more info about what I tried so far, I will appreciate your help, thnx
I am a beginner to analog IC.I have read some theory but when it comes to simulation, I just get lost, even at the DC biasing stage. I am trying to design a simple (miller) opamp, which will give me a gain of like 200(either one or 2 stages), i am not worried about the freq response or comp. all I want is a diff amp with this gain a good input and output CM range . I am using cadence TSMC .25u tech. Vdd=2.5V Vss=0, two Pmos load on the top, two diff Nmos below it and nmos current mirror at the bottom. tail current 20u, so current in each arm 10u. I wanted to have like Vod=.4, I calculate all the W/l's for this much current and overdrive, but I cannot seem to control the drain voltages. how do you figure out the drain voltages? from my calculation which seem right on paper, but on cadence get one or other in linear or reverse. and I am not even sure if I have the right values of Kn,Kp and Vth's (109.7uV/AA, -25.5uV/AA, Vthp=-.53, Vth,n=.495V) what am I doing wrong? how do you ideally start the design process?? (I have attached a hand made ckt file also, Pls dont laugh at the drawing)
Can someone guide me in details as how to bias and calculate W/L, what controls the drain voltages, and stuff)? I would really appreciate it. I try each time and give up frustrated...(hope its the right place to post this) let me know if you need more info about what I tried so far, I will appreciate your help, thnx