Help me design a 9999 counter in Verilog

[yatta]

Hi. I'm undertaking a project in school and i've been tasked to design a 9999 counter. I'm new to verilog and thus, i need some help regarding the counter.

I'm trying to use if-else and i'm stuck at this part:

if(counter<4'd10)
begin
digit1=counter;
end

else if (counter>=4'd10 && counter<4'd100)
begin
digit1=counter/4'd10;
digit2=counter%4'd10;
end

else if (counter>=4'd100 && counter<4'd1000)
begin
digit1=counter/4'd100;



i'm not exactly sure how to extract the 2nd digits if the numbers range from 100-999. your help would be much appreciated. Thanks

 

[lordsathish]

Re: 9999 counter=(

hey i think this way of codingwon realise your counter...

try using this...
module counter(clk,rst,q);
input clk,rst;
output [13:0]q;
reg [3:0]q;

always@(posedge clk or negedge rst)
begin
if(!rst)
q<=13'd0;
else if(q==13'd9999)
q<=13'd0;
else
q<=q+13'd1;
end

endmodule

 

[yatta]

Re: 9999 counter

I'll give it a try... thanks loads=)